Developer Events
Future Events, Webinars and Hackathons
The Cloud Native Computing Foundation* flagship conference gathers adopters and technologists from leading open source and cloud-native communities. KubeCon + CloudNativeCon is the premier vendor-neutral cloud-native event that brings together the industry’s most respected experts and key maintainers behind the most popular projects in the cloud-native ecosystem.
April 1–4, 2025; London, UK
Build a large language model (LLM) application using the power of AI PC processing, tapping the native capabilities of Intel® Core™ Ultra processors for running AI locally. The session shows how to develop a Python* back end with a browser extension that compactly summarizes web page content. The exercise showcases the Intel® hardware and software that makes it possible to run LLMs locally.
April 16, 2025, 9:00 a.m. Pacific Daylight Time (PDT)
Open Platform for Enterprise AI (OPEA) provides the building blocks for enterprise applications, including LLMs, prompt engines, and data stores, based on retrieval augmented generation (RAG) principles. This workshop guides you through the processes of building and deploying enterprise-grade generative AI (GenAI) applications for launching on Amazon Web Services (AWS)*. Explore the capabilities of OPEA to streamline development of a RAG pipeline using structured, repeatable techniques.
April 22, 2025, 9:00 a.m. – 12:00 p.m. Pacific Daylight Time (PDT)
Run DeepSeek* models on Intel® hardware to experience the advantages of open source freedom, advanced reasoning capabilities, and a lightweight footprint. This webinar uses the vLLM inferencing engine and the ChatQnA application to illustrate the essential qualities of DeepSeek. The session also demonstrates the low cost of running AI on the CPUs of Intel® Xeon® processors and Intel® Gaudi® AI accelerators, a clear alternative to GPUs that is efficient and cost-effective.
Gain familiarity with the Open Platform for Enterprise AI (OPEA), which is used to power the ChatQnA application and provides a useful tool to show the fundamentals of constructing chatbots. Developers viewing the tutorials provided can see how the DeepSeek models can be run on relatively modest hardware and get excited about the potential for running successfully on Intel hardware.
April 23, 2025, 9:00 a.m. Pacific Daylight Time (PDT)
This summit is the premier event for open source developers, technologists, and community leaders to collaborate, share information, solve problems, and gain knowledge, furthering open source innovation and ensuring a sustainable open source ecosystem. It is the gathering place for open source code and community contributors.
June 23–25, 2025; Denver, CO
The Cloud Native Computing Foundation* flagship conference gathers adopters and technologists from leading open source and cloud-native communities. KubeCon + CloudNativeCon is the premier vendor-neutral cloud-native event that brings together the industry’s most respected experts and key maintainers behind the most popular projects in the cloud-native ecosystem.
November 10–13, 2025; Atlanta, GA
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Past Events
Discover the most effective techniques for creating apps—from simple to complex—for AI PCs, including large language models (LLMs). This workshop gives you a solid foundation for understanding Intel® Tiber™ AI Cloud, using Intel® Gaudi® AI accelerators and the Intel® Distribution of OpenVINO™ toolkit for AI models for deploying models on AI PCs. The session will also cover SynapseAI software for Intel Gaudi processors using Python* and PyTorch*.
March 27, 2025, 9:00 a.m.–12:00 p.m. Pacific Standard Time (PST)
Retrieval augmented generation (RAG) is widely recognized as an effective means to empower knowledge workers with low-hallucination results, maximize privacy and security, improve scalability, and foster explainability. Explore the proven techniques for deploying a trusted RAG system versus building a complex, difficult-to-manage approach.
March 26, 2025, 9:00 a.m. Pacific Daylight Time (PDT)
Learn master techniques for building advanced retrieval augmented generation (RAG) applications with Intel® Gaudi® AI accelerators, exploring traditional and agentic methods.
March 20, 2025, 9:00 a.m. Pacific Standard Time (PST)
AI agents add new capabilities for responding intelligently to queries, data collection, and decision-making, assisted by additional functionality from Open Platform for Enterprise AI (OPEA). Retrieval augmented generation (RAG) bolstered by OPEA grants another level to agent design, strengthened by Intel® Gaudi® AI accelerators and Intel® Xeon® processors. This session provides guidance on designing, building, customizing, and deploying AI agents for hierarchical, multiagent systems with greater success than non-agentic generative AI (GenAI) solutions.
March 19, 2025, 9:00 a.m. Pacific Daylight Time (PDT)
See what the latest AI tools from Intel can do to improve your AI development tasks and extend your coding capabilities. Expand the boundaries of the latest optimized models and frameworks driving AI efficiency, boosting scaling, and enhancing generative AI (GenAI) quantization and inference.
March 12, 2025, 9:00 a.m. Pacific Daylight Time (PDT)
Join us for this immersive, hands-on session where you’ll delve into the world of local large language models (LLMs) and discover how to harness their power for retrieval augmented generation (RAG) based AI applications.
March 4, 2025, 9:00 a.m. Pacific Daylight Time (PDT)
Developers will learn how to build local agents for a variety of tasks, including research assistance data management, UI design, and natural language processing tasks. We will focus on laptops equipped with the Intel® Core™ Ultra processor and highlight tips for optimizing high performance and integrating with external sources.
February 27, 2025, 9:00 a.m.–11:00 a.m. Pacific Standard Time (PST)
The combined scalability and efficiency of Intel® hardware and the flexible power of the IBM watsonx* AI portfolio make an ideal platform for gaining the most from retrieval augmented generation (RAG).
February 26, 2025, 9:00 a.m. Pacific Standard Time (PST)
Description: Intel® Gaudi® AI accelerators streamline the creation of generative AI (GenAI) solutions, including deployment and optimization, working with state-of-the-art multimodal models.
February 20, 2025, 9:00 a.m. Pacific Standard Time (PST)
This webinar is with our collaborator, Amazon Web Services (AWS)*. We cover how AWS contributed bedrock and OpenSearch microservices while working with Intel.
February 19, 2025, 9:00 a.m. Pacific Standard Time (PST)
Description: Gain hands-on proficiency using Intel® Gaudi® accelerators, focusing on fine-tuning large language models (LLMs) and optimizing inference techniques.
February 13, 2025, 9:00 a.m. Pacific Standard Time (PST)
AI PCs are increasingly enabling new capabilities for portability and local AI implementations. Learn how the Web Neural Network (WebNN) API is standardizing interactions with CPUs, GPUs, and NPUs to gain optimal performance and predictable behavior.
Febuary 06, 2025, 9:00 a.m.–11:00 a.m. Pacific Standard Time (PST)
This presentation explores the integration of Open Platform for Enterprise AI (OPEA) with Kubernetes*, emphasizing streamlined deployment and scalability of AI models, specifically the retrieval augmented generation (RAG) pipeline.
January 29, 2025, 9:00 a.m. Pacific Standard Time (PST)
Each winning team will present its blue-ribbon project—built, tested, and optimized in the Intel® Tiber™ Developer Cloud using Intel’s latest hardware and AI software optimizations.
December 18, 2024, 9:00 a.m. Pacific Standard Time (PST)
Overcome the challenges of optimizing and deploying large language models on hardware that has limited computational resources.
December 11, 2024, 9:00 a.m. Pacific Standard Time (PST)
Learn how to use the GPU and NPU, in combination with OpenVINO™ toolkit, to develop, optimize, and deploy image-based generative AI (GenAI) models—such as Stable Diffusion and Latent Consistency Models—using multimodal learning.
December 11, 2024, 9:00 a.m. Pacific Standard Time (PST)
This immersive, hands-on session shows you how to harness the power of RAG (retrieval augmented generation) to enhance local large language models (LLMs). You can follow the examples and code using Intel® Tiber™ AI Cloud.
November 21, 2024, 9:00 a.m.–11:00 a.m. Hawaii-Aleutian Standard Time (HST)
Use the Web Neural Network API (WebNN) to achieve near-native AI inference performance and power characteristics from CPU, GPU, and NPU clients through the API’s implementation in Chromium-based browsers such as Chrome* and Edge.
November 20, 2024, 9:00 a.m. Pacific Standard Time (PST)
Understand techniques for building advanced retrieval augmented generation (RAG) applications with Intel® Gaudi® AI accelerators, exploring traditional and agentic methods.
November 19, 2024, 9:00 a.m. Pacific Standard Time (PST)
Discover how to take maximum advantage of the diffusion models with OpenVINO™ toolkit and the enhanced version of the Intel® Tiber™ AI Cloud.
November 14, 2024, 9:00 a.m.–11:00 a.m. Hawaii-Aleutian Standard Time (HST)
Learn how Open Platform for Enterprise AI (OPEA) is driving interoperability across a diverse and heterogeneous ecosystem to accelerate business-ready, secure, cost-effective generative AI (GenAI) deployments.
November 13, 2024, 9:00 a.m. Pacific Standard Time (PST)
This workshop suggests best practices for improving multimodal inference and explores Intel® Gaudi® software capabilities for handling text and image modalities.
November 12, 2024, 9:00 a.m.–11:00 a.m Pacific Standard Time (PST)
The Cloud Native Computing Foundation (CNCF)* flagship conference gathers adopters and technologists from leading open source and cloud native communities in Salt Lake City, Utah. Intel is a sponsor. Join our CNCF Graduated and Incubating Projects as the community gathers for four days to further the education and advancement of cloud native computing.
November 12–15, 2024, 8:00 a.m.–6:00 p.m. Mountain daylight time (MDT)
Harness enterprise-grade practices for building and deploying generative AI (GenAI) solutions, coupled with the expertise of Open Platform for Enterprise AI (OPEA) and the solid role played by Intel® Gaudi® accelerators and Intel® Xeon® Scalable processors.
November 6, 2024, 9:00 a.m. Pacific daylight time (PDT)
Gain hands-on proficiency using Intel® Gaudi® accelerators, focusing on fine-tuning large language models (LLMs) and optimizing inference techniques.
November 5, 2024, 9:00 a.m.–11:00 a.m. Pacific Standard Time (PST)
The recurrence of large language model (LLM) hallucinations bedevils developers, as they represent between 1% and 4% of the generative AI (GenAI) production rate, even from the best models. Discover proven methods of dealing with this issue.
October 30, 2024, 9:00 a.m. Honolulu daylight time (HDT)
This workshop is a detailed look into generative AI on the new era of AI PC. Learn how to use AI acceleration capabilities for generative AI (GenAI) across CPUs, GPUs, and NPUs. Designed for developers, this session is a comprehensive overview of using GPUs and NPUs for image-based generative AI and using the OpenVINO™ toolkit to optimize the implementation and deployment of AI models such as Stable Diffusion*, latent consistency models, and more.
October 23, 2024, 10:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Advances in AI have been paralleled by those in top-notch development tools, including the latest open-source tools released by Intel, such as AI libraries Intel® oneAPI Deep Neural Network Library (oneDNN), Intel oneAPI Data Analytics Library (oneDAL), and Intel® oneAPI Collective Communications Library (oneCCL), which establish a solid performance foundation.
October 16, 2024, 9:00 a.m. Pacific daylight time (PDT)
Discover performance techniques for using SYCL* to optimize acceleration for HPC systems.
October 15, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
This webinar showcases OpenVINO™ toolkit, which enables generative AI (GenAI) applications with powerful capabilities and enhanced integration and deployment.
October 9, 2024, 9:00 a.m. Pacific daylight time (PDT)
Join us for an in-depth showcase of the oneAPI specification and open source projects that implement it. These projects are designed to enable developers to use a single code base across multiple accelerators and architectures to enable AI, HPC, edge compute, and more.
October 9–10, 2024, 9:00 a.m.–5:00 p.m. Central daylight time (CDT)
Discover effective techniques for harnessing Hugging Face* tools to unlock the power of AI PCs.
September 26, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
Gain amazing performance with the Intel® Distribution for Python* and oneAPI in this hands-on workshop.
September 24, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
Bringing AI Everywhere, the Intel AI Summit series brings the future of AI to developers with hands-on technical training, thought leadership, and connection to industry peers. Learn how Intel’s software and hardware portfolios can help power your AI solutions and accelerate your AI journey at scale.
Location: Paris, France
Date: Tuesday, September 17, 2024
Time: 16:00 - 21:00 CET
OpenVINO™ toolkit excels at optimizing Open Neural Network Exchange (ONNX) models, making it an ideal tool for coaxing the best behavior from a heterogeneous network, including operations involving multithreading inference, model quantization, and graph partitioning.
September 11, 2024, 11:00 a.m. Pacific daylight time (PDT)
Discover effective techniques for deploying LLMs to AI PCs and achieving top performance. Using LLMs as a model for building GenAI solutions, this session explains NPU architecture, the significance of LLMs, and the use of the Intel® NPU Acceleration Library.
September 11, 2024, 9:00 a.m. Pacific daylight time (PDT)
Learn the essential techniques to use with Intel® Gaudi® AI accelerators to balance distributed AI workloads, meet data center challenges, and improve advances in efficiency and performance.
September 4, 2024, 9:00 a.m. Pacific daylight time (PDT)
Explore the deployment of large language models (LLM). Learn about the practicality and advantages of client PCs and small form-factor machines at the edge with a focus on implementing a conversational voice agent. Delve into the process of efficiently deploying LLMs on resource-constrained devices by examining techniques such as quantization and optimization through the OpenVINO™ toolkit. Additionally, watch how a user-friendly interface built with Gradio can enhance the agent's accessibility and usability.
August 29, 2024, 10:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Put Intel® Gaudi® 2 AI accelerator through its paces, streamlining training and inference and enhancing generative AI (GenAI) integration and deployment.
August 28, 2024, 9:00 a.m. Pacific daylight time (PDT)
Bringing AI Everywhere, the Intel AI Summit series brings the future of AI to developers with hands-on technical training, thought leadership, and connection to industry peers. Learn how Intel’s software and hardware portfolios can help power your AI solutions and accelerate your AI journey at scale.
Location: Toronto, Ontario
Date: Thursday August 22, 2024
Time: 1:00 PM - 5:00 PM EDT
Tune and optimize AI applications on Intel® hardware.
August 22, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
Get in-depth performance insights for deep learning model–based applications targeting CPU, GPU, and NPU.
August 14, 2024, 9:00 a.m. Pacific daylight time (PDT)
Get a comprehensive evaluation of Intel® CPU and GPU performance within the cutting-edge context of federated learning.
August 7, 2024, 9:00 a.m. Pacific daylight time (PDT)
Build, optimize, and deploy AI apps on an AI PC by taking advantage of diverse processors, including CPUs, GPUs (both integrated and discrete), and NPUs.
August 1, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
Join us to learn how Hugging Face and its Optimum for Intel are shaping the future of generative AI (GenAI) by simplifying and optimizing AI inference through the Transformers library.
With just five lines of code, you can now achieve efficient and flexible GenAI. A how-to session will showcase our fundamental efforts in 2023 by bringing optimized workloads such as Stable Diffusion*, large language models, and audio transcription models to the AI developer community.
July 31, 2024, 10:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn the best practices and tools for building high-performance generative AI applications on budget-friendly Intel® GPUs.
July 31, 2024, 9:00 a.m. Pacific daylight time (PDT)
This course introduces the FPGA device in an easy-to-understand manner for people who are completely new to the world of FPGAs. This instructor-led class is taught in a virtual classroom over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera® FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class.
July 26, 2024 09:30-14:00 CET.
Learn how to overcome the challenges of systems with multiple GPUs.
July 25, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Altera® FPGA Timing Closure: Lecture class. Your time during this workshop will mostly be spent using Intel® Quartus® Prime Software to practice timing closure techniques. This instructor-led class is taught in a virtual classroom over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed.
July 24, 2024 09:00-13:30 PST.
This class teaches the techniques used by design specialists to close timing on designs that push the limits of performance. This instructor-led class is taught in a virtual classroom over one half day of instruction. This class consists of a presentation only, along with the chance to ask questions of the instructor throughout the presentation. To get practice using what you have learned, sign up for the Altera® FPGA Timing Closure: Hands-On Lab class.
July 23, 2024 09:00-13:30 PST.
In this class, learn about the Nios® V processor, the next-generation softcore processor from Intel based on the open source RISC-V* instruction set and designed for Intel® FPGA devices. This instructor-led class is taught in a virtual classroom over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera® FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed.
July 22, 2024 07:30-12:00 CET.
Learn how to run training and inference on Intel® Gaudi® 2 AI accelerators, including how to migrate your models from a GPU.
July 17, 2024, 9:00 a.m. Pacific daylight time (PDT)
This class teaches the basics of how to build embedded system designs quickly for Altera® FPGA devices using the Platform Designer system-level integration tool, part of Intel® Quartus® Prime Software. This instructor-led class is taught in a virtual classroom over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class.
July 17, 2024 07:30-12:00 CET.
In this class, learn how to use Intel® Quartus® Prime Pro Edition Software and correlate steps to the general flow of an FPGA design process. You will employ the Intel Quartus Prime Software features to help you achieve design goals faster. You will also learn to plan and manage I/O assignments for your target device. This instructor-led class is taught in a virtual classroom over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera® FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed.
July 15-16, 2024 09:30-14:00 CET.
This workshop is a follow-on to the Altera® FPGA Timing Analysis: Lecture class. The class begins with a very short review of SDC concepts, followed by a long period of time to work through hands-on lab exercises. This instructor-led class is taught in a virtual classroom over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. To attend a comprehensive presentation about timing analysis, sign up for the Altera FPGAs Timing Analysis: Lecture class.
July 12, 2024 09:00-13:30 PST.
In this class, learn how to constrain and analyze a design for timing using the Timing Analyzer in Intel® Quartus® Prime Pro Edition Software v. 22.1. This instructor-led class is taught in a virtual classroom over one half day of instruction. This class consists of a presentation only, along with the chance to ask questions of the instructor throughout the presentation. To get practice using what you have learned, sign up for the Altera® FPGA Timing Analysis: Hands-On Lab class.
July 11, 2024 09:00-13:30 PST.
Learn strategies for implementing a RAG system capable of transforming vast amounts of data into accessible, relevant, and accurate results.
July 10, 2024, 9:00 a.m. Pacific daylight time (PDT)
Learn how to build computer vision and anomaly detection applications for AI inference solutions. Use the open source Anomalib library for unsupervised learning with imbalanced datasets to handle rare defects in real time. Improve quality control in manufacturing, healthcare, agriculture, and more. See a robot in action. Get a recap of the Visual Anomaly and Novelty Detection (VAND) 2.0 challenge at the Computer Vision and Pattern Recognition Conference (CVPR).
June 27, 2024, 10:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn how the AI integration company cracked the code on trustworthy, high-performance Large Language Model (LLM) applications, achieving 2x throughput gains, cost efficiencies, and more.
June 26, 2024, at 9:00 a.m. Pacific daylight time (PDT)
This workshop explores ways to use the Intel® Tiber™ Developer Cloud to examine the Diffusers library for pretrained diffusion models for multi-model, generative AI.
June 25, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
This workshop demystifies Intel® NPUs, providing examples with large language models (LLMs) and case studies. The fundamental architecture of NPUs is explained and the capabilities of the technology revealed, offering a clear picture of the role of neural processors in an AI system and the acceleration benefits.
June 24, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
Build AI solutions with the Intel® Tiber™ Developer Cloud using the latest Intel hardware and software.
June 20, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
Learn how to effectively integrate large language models (LLMs) with Intel® NPUs, one of the compute engines available in the new AI PC from Intel.
June 12, 2024, 9:00 a.m. Pacific daylight time (PDT)
Learn how to use the OpenVINO™ toolkit on the new AI PC to build flexible, low-power, AI-assisted apps that you can take on the go, without needing the internet or the cloud.
June 5, 2024, 9:00 a.m. Pacific daylight time (PDT)
Dive into the new era of AI PCs with their unique AI acceleration capabilities that span across CPUs, GPUs, and NPUs. This session provides a comprehensive overview of using the NPU for AI inference tasks and uses OpenVINO™ toolkit to optimize the implementation and deployment of AI applications. Experience live demos showcasing the performance and power efficiency of AI applications on the AI PC. Learn how to use OpenVINO toolkit to optimize hardware use for AI inference, enhancing the efficiency and innovative potential of their AI projects.
May 23, 2024, 10:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Find out how a collaboration between Intel and AI startup Bilic has propelled Bilic’s business progression and development, setting it up for increased scale, innovation, and market excellence.
May 22, 2024, 9:00 a.m. Pacific daylight time (PDT)
The oneAPI solution delivers a unified programming model to simplify development across diverse architectures. When combined with SYCL*, the Intel® oneAPI DPC++ Library (oneDPL) provides high-productivity APIs to developers.
May 21, 2024, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
Visit Intel at booth FP38 for a chance to win an AI PC.
May 21–23, 2024, 8:00 a.m.–6:00 p.m. Pacific daylight time (PDT)
This introduction—for novices to Intel® Tiber™ Developer Cloud—prepares you to get started, learn the capabilities and organization of the environment, and become acquainted with key resources.
May 16, 2024, 9:00 a.m.–10:30 a.m. Pacific daylight time (PDT)
Learn how to significantly enhance LLM performance on Intel® platforms by taking advantage of the features of two powerful Intel-optimized libraries.
May 8, 2024, 9:00 a.m. Pacific daylight time (PDT)
In this workshop, we’ll discuss intriguing new dilemmas in the generative AI (GenAI) space: Will large language models (LLM) fit on small form-factor machines? Smaller LMs versus LLMs? Where is the sweet spot for local inference? We’ll discuss the era of LLM compression, including int8, int4, and 1-bit LLM models, and how it can be more effective to work on complex deep learning models and big data processing with GPUs, NPUs, and CPUs.
April 30, 2024, 10:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
This course introduces the FPGA device in an easy-to-understand manner for people who are completely new to the world of FPGAs. This instructor-led class is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera* FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class.
April 25, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Find out how this company used the Intel® AI software portfolio of ready-to-use reference kits to optimally uncover the right customers at the right time.
April 24, 2024, 9:00 a.m. Pacific daylight time (PDT)
Join AI experts from Landing AI and Intel Labs to learn how to minimize bias and hallucinations in multimodal large language models (LLM) that can handle diverse data types.
April 23, 2024, 10:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn efficient coding techniques for writing synthesizable Verilog HDL for Altera* FPGAs and complex programming logic devices (CPLD). This instructor-led class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera* FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No set up is needed.
April 23 - 24, 2024, 9:30 a.m.-2:00 p.m. central European time (CET)
Learn how to design with these FPGAs using the Intel® Quartus® Prime software and how to develop software for these devices. At the completion of the course, you will have the knowledge necessary to immediately start using Altera* SoC FPGA devices in your own designs or on development kits. This instructor-led class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera* FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No set up is needed.
April 18 - 19, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This course introduces the Signal Tap embedded logic analyzer, one of the many debug tools included in Intel® Quartus® Prime Software. This instructor-led class is taught in a virtual classroom with over one half-day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera* FPGA Training that is preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No set up is needed.
April 17, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This summit is the premier event for open source developers, technologists, and community leaders to collaborate, share information, solve problems, and gain knowledge, furthering open source innovation and ensuring a sustainable open source ecosystem. Intel will have speakers and a booth.
April 16-18, 2024, 9:00 a.m.-5:00 p.m. Pacific daylight time (PDT)
Learn the basics for building embedded system designs quickly for Altera* FPGA devices using the Platform Designer system-level integration tool, which is part of the Intel® Quartus® Prime Software. This instructor-led class is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera* FPGA Training that is preconfigured with the necessary tools. Information required to connect to the remote system will be provided during the class.
April 16, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This class is a general introduction to Verilog HDL and its use in programmable logic design, covering the basic constructs used in simulation and synthesis environments. This instructor-led class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera* FPGA Training that is preconfigured with the necessary tools. Information required to connect to the remote system will be provided during the class. No set up is needed.
April 16 - 17, 2024, 9:30 a.m.-2:00 p.m. central European time (CET)
Learn how to use the Intel® Quartus® Prime Pro Edition Software and correlate these steps to the general flow of an FPGA design process. Employ the Intel® Quartus® Prime software features to help you achieve design goals faster. Learn how to plan and manage I/O assignments for your target device. This instructor-led class is taught in a virtual classroom over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera* FPGA Training that is preconfigured with the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
April 11 - 12, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in simulation and synthesis environments. This instructor-led class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera* FPGA Training that is preconfigured with the necessary tools. Information required to connect to the remote system will be provided during the class. No set up is needed.
April 9 - 10, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Use ISO3DFD on Intel® Developer Cloud to optimize routines for Intel® Data Center GPU Max Series.
March 28, 2024, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
This course introduces the FPGA in an easy-to-understand manner for people who are new to to these devices. It is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class.
March 28, 2024, 9:30 a.m.-2:00 p.m. central European time (CET)
How can a retail business adopt generative AI to accelerate its growth? Join e.l.f.* Beauty and Iterate.a*i to learn how a low-code AI platform can quickly deploy large language models (LLM) to transform a retail business and improve customer engagement and revenue.
What you will learn:
- The good and the bad—the reality of generative AI for retail.
- How to choose the right generative AI initiatives for impactful outcomes.
- Best practices on how to build and deploy LLMs.
- Retrieval augmented generation (RAG) and LLMs in action for social media.
Speakers:
- Brian Sathianathan, cofounder and CTO of Iterate.ai
- Ekta Chopra, chief digital officer, e.l.f. Beauty
March 27, 2024, 10:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn how to fine-tune the nanoGPT model on a cluster of CPUs on Google Cloud Platform* service using an Intel® Optimized Cloud Module.
March 27, 2024, 9:00 a.m. Pacific standard time (PST)
This workshop is a follow on to the Intel® FPGA Timing Closure: Lecture class. Your time during this workshop will mostly be spent using the Intel® Quartus® Prime Software to practice timing closure techniques. This class is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Inte® FPGA Training that's preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
March 27, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Discover GPU optimization techniques using Intel® hardware and Intel® Developer Cloud.
March 26, 2024, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn techniques used by design specialists to close timing on designs that extend the limits of performance. This class provides chances to ask the instructor questions throughout the presentation. For practice using what you learned, sign up for the Intel® FPGA Timing Closure: Hands-on Lab.
March 26, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Analysis–Lecture class. (To attend a comprehensive presentation about timing analysis, sign up for the Timing Analysis–Lecture class.) The lab includes a brief review of the SDC constraints learned in the previous class. This lab is taught in a virtual classroom with over one half day of instruction. It begins with a short review of concepts, followed by a long period of time to work on hands-on lab exercises. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training that's preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
March 20, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This course introduces the FPGA in an easy-to-understand manner for people who are new to to these devices. It is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class.
March 19, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
The Cloud Native Computing Foundation* flagship conference gathers adopters and technologists from leading open source and cloud-native communities. Intel is a platinum sponsor and has a booth at the event.
March 19-22, 2024, 8:00 a.m.-6:00 p.m. central European time (CET)
This course introduces the FPGA in an easy-to-understand manner for people who are new to to these devices. It is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class.
March 18, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Discover the full capabilities of Intel® Developer Cloud for working with large language models (LLM) and Stable Diffusion* models.
March 14, 2024, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
The Nios® V/m processor is Intel’s next-generation soft-core processor based on the open source RISC-V* instruction set, designed for Intel® FPGA devices. This class is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training that's preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
March 14, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn efficient coding techniques for writing a synthesizable Verilog HDL for Intel® FPGAs and complex programmable logic devices (CPLD). This class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
March 12 - 13, 2024, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
The Nios® V/m processor is Intel’s next-generation soft-core processor based on the open source RISC-V* instruction set, designed for Intel® FPGA devices. This class is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training that's preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
March 12, 2024, 9:30 a.m.-2:00 p.m. central European time (CET)
Learn how the new features of Intel® oneAPI DPC++ Library (oneDPL)—Parallel STL offload, improved random number generation, and dynamic device selection—offer developers more opportunity to accelerate performance, particularly when targeting hardware accelerators like GPUs.
March 6, 2024, 9:00 a.m. Pacific standard time (PST)
Learn how to assess and implement additional postmigration steps. Tune your application for performance portability across hardware from different vendors.
February 28, 2024, 9:00 a.m. Pacific standard time (PST)
This course introduces the FPGA in an easy-to-understand manner for people who are new to to these devices. It is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class.
February 28, 2024, 9:30 a.m.-2:00 p.m. Central European Time (CET)
Learn how to access a cluster of the latest Intel® hardware through Intel’s brand-new cloud platform–Intel® Developer Cloud–to accelerate and scale an AI and HPC application workload. You will be able to access free training content on JupyterLab, launch instances from the Intel Developer Cloud console, and access instances via SSH. Attendees will also receive a free coupon for evaluating the platform.
February 28, 2024, 1:30 p.m.-2:30 p.m. Japan standard time (JST)
This course introduces the FPGA in an easy-to-understand manner for people who are new to to these devices. It is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class.
February 26, 2024, 9:00 a.m.-1:30 p.m. Pacific standard time (PST)
Join this webinar to hear Accenture* share best practices, considerations, and architectures for constructing a self-managed Generative AI (GenAI) platform capable of hosting a myriad of applications.
February 22, 2024, 10:00 a.m.–11:00 a.m. Pacific standard time (PST)
Learn how to use the Intel® Quartus® Prime Pro Edition Software and correlate these steps to the general flow of an FPGA design process. You will employ the Intel Quartus Prime Software features to help you achieve design goals faster. Learn to plan and manage I/O assignments for your target device. This class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
February 22-23, 2024, 9:00 a.m.-1:30 p.m. Pacific standard time (PST)
Get an insider’s view of the 2024.0 release, plus engage in a live Q&A with Intel® software experts.
February 21, 2024, 9:00 a.m. Pacific standard time (PST)
Take advantage of pandas, NumPy, and PyTorch* to improve the performance of Python.
February 20, 2024, 9:00 a.m. – 11:00 a.m., Pacific standard time (PST)
This class is a general introduction to the Verilog language, its use in programmable logic design, and covers the basic constructs used in the simulation and synthesis environments. It is taught in a virtual classroom in over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
February 20-21, 2024, 9:00 a.m.-1:30 p.m. Pacific standard time (PST)
This workshop is a follow-up to the Intel® FPGA Timing Closure: Lecture class. Your time will mostly be spent using the Intel® Quartus® Prime Software to practice timing closure techniques. This class is taught in a virtual classroom with over one half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
February 16, 2024, 9:00 a.m.-1:30 p.m. Pacific standard time (PST)
Learn techniques used by design specialists to close timing on designs that extend the limits of performance. This class is taught in a virtual classroom with over one half day of instruction. It is a presentation only and gives the chance to ask the instructor questions throughout the presentation. For practice using what you learned, sign up for the Intel® FPGA Timing Closure: Hands-on Lab.
February 15, 2024, 9:00 a.m.-1:30 p.m. Pacific standard time (PST)
Learn how to take advantage of Intel®-optimized machine learning and deep learning frameworks and libraries—PyTorch*, TensorFlow*, scikit-learn*, and XGBoost—in the popular CSP platform.
February 14, 2024, 9:00 a.m. Pacific standard time (PST)
Learn how to design with these FPGAs using the Intel® Quartus® Prime Software and how to develop software for these FPGAs. At the completion of the course, you will have the knowledge necessary to immediately start using Intel® SoC FPGA devices in your own designs or development kits. This class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
February 13-14, 2024. 9:00 a.m.-1:30 p.m. Pacific standard time (PST)
Learn how to use the Intel® Quartus® Prime Pro Edition Software and correlate these steps to the general flow of an FPGA design process. You will employ the Intel Quartus Prime Software features to help you achieve design goals faster. Learn to plan and manage I/O assignments for your target device. This class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
February 13-14, 2024, 9:30 a.m.-2:00 p.m. central European time (CET)
Learn how to offload Python* data and workloads to any SYCL* device, such as a GPU, with little effort.
February 7, 2024, 9:00 a.m. Pacific standard time (PST)
This session gives you the opportunity to ask questions directly to an Intel® FPGA expert and learn from others’ questions.
February 7, 2024, 9:00 a.m.-11:00 a.m. Pacific standard time (PDT)
This training covers simulator functionalities that include hardware and software inspection, dynamic system configuration, hardware modeling tools, scripting, and a rich set of other features. This class is over a half day of instruction in a virtual classroom. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that's preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
February 7, 2024, 9:00 a.m.-1:30 p.m. Pacific standard time (PT)
Get going with C++ with SYCL* in about 60 minutes so you can code for multiarchitecture platforms using a single programming language.
January 31, 2024, 9:00 a.m. Pacific standard time (PST)
Hugging Face* APIs let you optimize AI routines for Intel® hardware.
January 30, 2024, 9:00 a.m. – 11:00 a.m. Pacific standard time (PST)
This instructor-led class is taught in a virtual classroom over one half-day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training and preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. This course introduces the FPGA device in an easy-to-understand manner for people who are completely new to the world of FPGAs.
January 30, 2024, 9:30 a.m.-2:00 p.m. Central European Time (CET)
This instructor-led class is taught in a virtual classroom over one half-day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training and preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. This course introduces the FPGA device in an easy-to-understand manner for people who are completely new to the world of FPGAs.
January 29, 2024, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Speed up tasks such as data preprocessing at scale, training, and inference while gaining performance.
January 24, 2024, 9:00 a.m. Pacific standard time (PST)
This instructor-led class is taught in a virtual classroom over one half-day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training and pre-configured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. The Nios® V processor is Intel’s next generation soft-core processor based on the open source RISC-V instruction set, designed for Intel® FPGA devices.
January 23, 2023, 9:30 a.m.-2:00 p.m. Central European Time (CET)
This instructor-led class is taught in a virtual classroom over one half-day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training and preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. This instructor-led training for Intel® Simics® Simulator for Intel® FPGAs covers the functionalities for the simulator that include hardware and software inspection, dynamic system configuration, hardware modeling tools, scripting, and a rich set of other features.
January 18, 2024, 9:00 a.m.-1:30 p.m. Pacific time (PT)
This instructor-led class is taught in a virtual classroom over one half-day of instruction. The class begins with a very short review of concepts, followed by a long period of time to work hands-on lab exercises. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training and preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. To attend a comprehensive presentation about timing analysis, sign up for the Timing Analysis: Lecture class. This workshop is a follow on to the Intel® FPGA Timing Analysis: Lecture class. There will be a brief review of the SDC constraints learned in the previous class before starting the labs.
January 17, 2024, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Get an insider’s view of this release, plus engage in a live Q&A with Intel® software experts.
January 17, 2024, 9:00 a.m. Pacific standard time (PST)
This instructor-led class is taught in a virtual classroom over one half-day of instruction. This class consists of presentation only, along with the chance to ask questions of the instructor throughout the presentation. To get practice using what you have learned, sign up for the Intel® FPGA Timing Analysis: Hands-on Lab class. You will learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Software v. 22.1.
January 16, 2024, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn the principles and techniques of making your PyTorch* programs faster and more useable and performant with the framework’s just-in-time (JIT) compiler, TorchDynamo.
January 10, 2024, 9:00 a.m. Pacific standard time (PST)
This instructor-led class is taught in a virtual classroom over two half-days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training and preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. You will learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and CPLDs.
January, 9-10, 2024, 9:00 a.m.-1:30 p.m. Pacific time (PT)
This instructor-led class is taught in a virtual classroom over one half-day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training and preconfigured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. This class will teach you how to design with Intel® FPGA SoC using the Intel Quartus® Prime Software and how to develop software for these devices. It will cover the hard processor system (HPS) architecture for Intel® Stratix® 10, Intel® Arria® 10, Cyclone® V, and Arria® V devices, including an overview of the Arm* Cortex*-A53 and A-9.
9:30 a.m.-2:00 p.m. Central European Time (CET)
Join Intel at numerous locations at the CES show in January.
January 7-10, 2024, 8:00 a.m. Pacific standard time (PST)
This course introduces the FPGA device in an easy-to-understand manner for people who are completely new to FPGAs. This instructor-led class is taught in a virtual classroom with over a half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
December 14, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. This instructor-led class is taught in a virtual classroom with over a half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
December 14, 2023, 9:30 a.m. - 2:00 p.m. central European time (CET)
Learn how to build secure, scalable, and accelerated Kubeflow* pipelines on an Azure* Kubernetes* Service (AKS) cluster.
December 13, 2023, 9:00 a.m. Pacific standard time (PST)
The Nios® V/m processor is Intel’s next-generation soft-core processor that is based on the open source RISC-V instruction set and is designed for Intel® FPGAs. This instructor-led class is taught in a virtual classroom with over a half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
December 12, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Advance your understanding of SYCL* concepts in this hands-on coding workshop. It highlights techniques for achieving efficient results on modern architectures with diverse hardware systems.
December 12, 2023, 9:00 a.m. – 11:00 a.m. Pacific standard time (PST)
Learn the basics of how to build embedded system designs quickly for Intel® FPGA devices using the Platform Designer system-level integration tool, part of the Intel® Quartus® Prime Software. This instructor-led class is taught in a virtual classroom with over a half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
December 12, 2023, 9:30 a.m. - 2:00 p.m. central European time (CET)
Learn how to accelerate GenAI* for the enterprise with small and nimble models. This webinar evaluates open source large language models (LLM) and how to move from a nimble to a fully adapted model.
December 7, 2023, 10:00 a.m. – 11:00 a.m. Pacific Standard Time (PST)
Accelerate rendering with tools included in the Intel® Rendering Toolkit, powered by oneAPI.
December 7, 2023, 9:00 a.m. to 11:00 a.m., Pacific standard time (PST)
Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and complex programmable logic devices (CPLD). This instructor-led class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
December 6 - 7, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Get an introduction to five AI reference solutions that are tailor-made to solve business problems across a variety of industries, delivering higher accuracy and better performance while decreasing development cycles.
December 6, 2023, 9:00 a.m. Pacific standard time (PST)
This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. This instructor-led class is taught in a virtual classroom with over a half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
December 5, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Predict forest fire likelihoods using PyTorch and image analysis with Intel® Extension for PyTorch
November 30, 2023
9:00 am - 11:00 am PST
The Nios® V/m processor is Intel’s next-generation soft-core processor that is based on the open source RISC-V instruction set and is designed for Intel® FPGAs. This instructor-led class is taught in a virtual classroom with over a half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
November 30, 2023, 9:30 a.m. - 2:00 p.m. central European time (CET)
Get an insider’s view of the 2024.0 tools release and engage in a live Q&A with Intel® software experts on all things oneAPI.
November 29, 2023, 9:00 a.m. Pacific standard time (PST)
Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and complex programmable logic devices (CPLD). This instructor-led class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
November 27 - 28, 2023, 9:30 a.m. - 2:00 p.m. central European time (CET)
Find out how Lisbon-based research and development innovator Instituto de Engenharia de Sistemas e Computadores—Investigação e Desenvolvimento (INESC-ID) significantly sped up its computationally crushing bioinformatics application on the latest Intel® CPUs using oneAPI tools.
November 15, 2023, 9:00 a.m. Pacific Daylight Time (PDT)
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in simulation and synthesis environments. This instructor-led class is taught in a virtual classroom with over two half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel® FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
November 15 - 16, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
This workshop is a follow-on to the Intel® FPGA Timing Closure—Lecture class. Use the Intel® Quartus® Prime Software to practice timing closure techniques. This instructor-led class is taught in a virtual classroom with over a half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
November 14, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Learn techniques used by design specialists to close timing on designs that extend the limits of performance. This instructor-led class is taught in a virtual classroom with over a half day of instruction. This class is a presentation and provides chances to ask the instructor questions. To practice what you learned, sign up for the Intel® FPGA Timing Closure—Hands-on Lab that teaches techniques used by design specialists to close timing on designs.
November 13, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
At a time of great uncertainty for many industries, we gather policymakers, heads of state, and the founders and CEOs of technology companies and fast-growing startups, to ask a simple question: Where to next?
November 13-16, 2023, 9:00 a.m. - 5:00 p.m. Greenwich mean time (GMT)
Visit the Intel display in booth 617 at the international conference for high-performance computing (HPC), networking, storage, and analysis.
November 12-17, 2023, 9:00 a.m. - 5:00 p.m. mountain standard time (MST)
Learn how to embed large language models (LLMs) into your workflows for generative AI. This webinar covers guiding principles domain-specific use cases, architectural approaches, and common challenges.
November 9, 2023, 10:00 a.m. - 11:00 a.m. Pacific standard time (PST)
Learn how OpenMP* addresses the limitations of Fortran by providing the missing features to enable heterogeneous parallelism.
November 8, 2023, 9:00 a.m. Pacific standard time (PST)
This workshop is a follow-on to the Intel® FPGA Timing Analysis—Lecture class. It includes a brief review of the SDC constraints learned in the previous class. This instructor-led class is taught in a virtual classroom with over a half day of instruction. The class begins with a short review of concepts, followed by a long period of time to work on hands-on lab exercises. To perform the lab exercises, you will connect to a remote computer provided by Intel FPGA Training that is preconfigured with all the necessary tools. Information for connecting to the remote system will be provided during the class. No set up is needed.
November 07, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Elevate your skills for optimizing AI systems using MLOps components and practices.
November 7, 2023
9:00 am - 11:00 am PST
Learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software v. 22.1. This instructor-led class is taught in a virtual classroom with over a half day of instruction. This class is a presentation and provides chances to ask the instructor questions. To get practice using what you have learned, sign up for the Intel® FPGA Timing Analysis—Hands-on Lab class.
November 06, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Adopters and technologists from leading open source and cloud-native communities attend this Cloud Native Computing Foundation (CNCF) conference.
November 6-9, 2023, 9:00 a.m. central daylight time (CDT), Chicago, Illinois.
Explore how pairing MLOps components and AI optimizations can transform your AI systems from legacy to being performant, scalable, and efficient across every step of a production AI system’s lifecycle.
November 1, 2023, 9:00 a.m. Pacific Standard Time (PST)
This course introduces the FPGA device in an easy-to-understand manner for people who are new to the world of FPGAs. It introduces FPGAs, their architecture, the basic tools in Intel® Quartus® Prime software that is used for FPGA design. You will use a remote computer connected on a cloud-based platform for hands-on labs. No setup is needed.
.October 31, 2023, 9:00 a.m.-1:30 p.m. Pacific time (PT)
This class is a general introduction to the Verilog language and its use in programmable logic design, and covers the basic constructs used in both the simulation and synthesis environments. You will use a remote computer connected on a cloud-based platform for hands-on labs. No setup is needed.
October 26-27, 2023, 9:30 a.m.-2:00 p.m. Central European Time (CET)
Learn how to solve Fortran linear systems that target GPUs by using the Intel® oneAPI Math Kernel Library (oneMKL) and OpenMP*.
October 25, 2023, 9:00 a.m. Pacific Daylight Time (PDT)
Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and CPLDs. While the course focuses on the Intel® Quartus® Prime software, many concepts can be used with other synthesis tools. You will use a remote computer connected on a cloud-based platform for hands-on labs. No setup is needed.
.October 25-26, 2023, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Speed up, scale, and efficiently manage your cloud-based machine learning workloads for less cost and more resource use with a new solution from Intel and Microsoft.
October 18, 2023, 9:00 a.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Closure: Lecture class. Your time during this workshop will mostly be spent using the Intel® Quartus® Prime Software to practice timing closure techniques. You will use a remote computer connected on a cloud-based platform for hands-on labs. No setup is needed.
.October 18, 2023, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Join us in San Jose, California to experience some of the most potentially disruptive technologies and market-leading products, and collaborate with a community of experts.
October 17-19, 2023, 9:00 a.m. - 5:00 p.m. Pacific daylight time (PDT)
Learn about a seamless code migration with SYCLomatic.
October 17, 2023, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
This class teaches the techniques used by design specialists to close timing on designs that “push the envelope” of performance. This class is lecture only. There is a follow-on workshop class that is lab based.
October 17, 2023, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn how to use the Intel® Quartus® Prime Pro Edition software and correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected on a cloud-based platform for hands-on labs. No setup is needed.
October 17-18, 2023, 9:30 a.m.-2:00 p.m. Central European Time (CET)
Discover how to use device memory allocation and data movement to achieve top performance from Intel® GPUs.
October 12, 2023, 9:00 a.m.–11:00 a.m.
This class teaches you how to design with Intel® Stratix® 10 and Intel Agilex® 7 SoC FPGAs using the Intel Quartus® Prime software and how to develop software for these devices. You will use a remote computer connected on a cloud-based platform for hands-on labs. No setup is needed.
October 10-11, 2023, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Advance your coding ability with powerful Python* capabilities.
September 28, 2023, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
This class is an introduction to HDL and its use in programmable logic design, covering the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through VMware* for labs. No set up is needed.
September 28-29, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Get an overview of the new (and impressive) MLPerf* benchmarking results for the 4th gen Intel® Xeon® Scalable processors and how the results were accomplished.
September 27, 2023, 9:00 a.m. Pacific daylight time (PDT)
This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. You will use a remote computer connected through VMware* for labs. No set up is needed.
September 27, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn what an FPGA is and its basic features. Get a description of the development flow for an FPGA design. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
September 26, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and complex programmable logic devices (CPLD). You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
September 25-26, 2023, 9:00 a.m.-1:30 p.m. central European time (CET)
This workshop is a follow-on to the Intel® FPGA Timing Analysis–Lecture class. It includes a brief review of the SDC constraints learned in the previous class.You will use a remote computer connected through VMware* for labs. No set up is needed.
September 21, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Get a walk-through of how to profile memory-intensive workloads running on the 4th gen Intel® Xeon® CPU Max Series, the first and only x86-based processor with HBM.
September 20, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro software v21.3. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
September 20, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Engage with your peers and learn from the brightest minds in the industry how to use breakthroughs in hardware, software, services, and advanced technologies to speed development, drive innovation, and help hone your competitive edge.
September 19-20, 2023, 9:00 a.m. Pacific daylight time (PDT)
This premier European event for open source developers, technologists, and community leaders is a gathering place for open source code and community contributors.
September 19-21, 2023, 9:00 a.m. central European time (CET), in Bilbao, Spain and virtual
Learn how to use the latest TensorFlow* optimizations from Intel to get more out of your AI workloads on Intel® hardware.
September 13, 2023, 9:00 a.m. Pacific daylight time (PDT)
Delve into the most effective techniques for optimizing Intel® GPU performance.
September 12, 2023, 9:00 a.m.-11:00 a.m. Pacific Daylight Time (PDT)
Learn what an FPGA is and its basic features. Get a description of the development flow for an FPGA design. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
September 11, 2023, 9:00 a.m.-1:30 p.m. central European time (CET)
Learn what an FPGA is and its basic features. Get a description of the development flow for an FPGA design. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
August 31, 9:00 a.m.-1:30 p.m. Pacific Time (PT)
Get your questions answered about Intel® Fortran Compiler v2023.0 and get a sneak peek at version 2024.0 in this Q&A session with its developers.
August 30, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool that is part of the Intel® Quartus® Prime Software. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
August 30, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Predict the likelihood of forest fires using PyTorch* and image analysis with Intel® Extension for PyTorch*.
August 29, 2023, 9:00 a.m.–11:00 a.m. Pacific daylight time (PDT)
Learn how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool that is part of the Intel® Quartus® Prime Software. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
August 29, 9:00 a.m.-1:30 p.m. Central European Time (CET)
Learn how to create a design using Nios® V IP Suite in the Platform Designer for Intel® Quartus® Software. Program with software-building tools a development kit to use Nios® V processor. You will use a remote computer connected through VMware* for labs. No set up is needed.
August 24, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Closure–Lecture class. Use the Intel® Quartus® Prime Software to practice timing closure techniques. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
August 24, 9:00 a.m.-1:30 p.m. Central European Time (CET)
Learn a step-by-step approach for adding SYCL* support to your C++ code and migrating existing CUDA*-based implementations to SYCL.
August 23, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn to implement and configure the first-stage and second-stage bootloaders (based on U-Boot), and how to build and boot to Linux*. You will learn the boot stages of the Intel® SoC FPGA family. You will use a remote computer connected through VMware* for labs. No set up is needed.
August 23, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Learn techniques used by design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
August 23, 9:00 a.m.-1:30 p.m. Central European Time (CET)
Join a step-by-step tutorial on creating an intelligent retail queue-management system using the OpenVINO™ toolkit and YOLO* v8. Learn the process of integrating these powerful open source tools to develop an end-to-end solution that can be deployed in retail checkout environments.
August 22, 2023, 9:00 a.m.-10:00 a.m. Pacific daylight time (PDT)
Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and complex programmable logic devices (CPLD). You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
August 21-22, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Join us for multiple days of discovery and inspiration. Renowned industry experts will demystify the latest AI and oneAPI technologies, tools, trends, and techniques.
August 18, 2023, 9:00 a.m.-10:30 a.m. central daylight time (CDT): Onboarding day
August 21, 2023, 9:00 a.m.-5:30 p.m. CDT: Day 1
August 22, 2023, 9:00 a.m. -12:30 p.m. CDT: Day 2
This workshop is a follow-on to the Intel® FPGA Timing Closure–Lecture class. Use the Intel® Quartus® Prime Software to practice timing closure techniques. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
August 17, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Learn techniques used by design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
August 16, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Learn how to efficiently harness accelerators from different vendors that include Intel and NVIDIA* GPUs. Led by Rakshith Krishnappa, an experienced developer evangelist for HPC and oneAPI, the workshop delivers a step-by-step approach to migration.
August 10, 2023, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Escape vendor lock-in by migrating from CUDA* code to multiplatform C++ with SYCL* code.
August 10, 2023, 9:00 a.m. to 11:00 a.m. Pacific daylight time (PDT)
Learn additional (and more advanced) methods to run inference and training faster using the new and experimental features of Intel® Extension for PyTorch*.
August 9, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to use the Intel® Quartus® Prime Pro Edition software and correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected through VMware* for labs. No setup is needed.
August 9-10, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Learn what an FPGA is and its basic features. Get a description of the development flow for an FPGA design. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
August 9, 9:00 a.m.-1:30 p.m. Central European Time (CET)
This class is an introduction to HDL and its use in programmable logic design, covering the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through VMware* for labs. No set up is needed.
August 7-8, 9:00 a.m.-1:30 p.m. Central European Time (CET)
EII consists of a set of preintegrated ingredients that are optimized for Intel® architecture. It includes modules that enable data collection, storage, and analytics for time-series and video data, as well as the ability to act on these insights by sending downstream commands to tools or devices.
In this session, you will learn about key features and improvements in EII v4.0.0.
July 27, 2023, 7:30 a.m.-8:30 a.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Analysis–Lecture class. It includes a brief review of the SDC constraints learned in the previous class.You will use a remote computer connected through VMware* for labs. No set up is needed.
July 27, 9:00 a.m.-1:30 p.m. Central European Time (CET)
Learn to implement and configure the first-stage and second-stage bootloaders (based on U-Boot), and how to build and boot to Linux*. You will learn the boot stages of each Intel® SoC FPGA family. You will use a remote computer connected through VMware* for labs. No set up is needed.
July 26, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro software v21.3. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
July 26, 9:00 a.m.-1:30 p.m. Central European Time (CET)
Explore different types of quantization techniques that can be applied to deep learning models. Get an overview of the Neural Network Compression Framework (NNCF) and how it complements the OpenVINO™ toolkit to achieve outstanding performance.
July 25, 2023, 9:00 a.m.-10:00 a.m., Pacific daylight time (PDT)
This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. You will use a remote computer connected through VMware* for labs. No set up is needed.
July 25, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Learn to implement and configure the first-stage and second-stage bootloaders (based on U-Boot), and how to build and boot to Linux*. You will learn the boot stages of the Intel® SoC FPGA family. You will use a remote computer connected through VMware* for labs. No set up is needed.
July 25, 9:00 a.m.-1:30 p.m. Central European Time (CET)
This workshop is a follow-on to the Intel® FPGA Timing Analysis–Lecture class. It includes a brief review of the SDC constraints learned in the previous class. You will use a remote computer connected through VMware* for labs. No set up is needed.
July 20, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Experienced GFX developers can learn how the open source Intel® Embree library can improve running photorealistic rendering applications across a CPU and GPU.
July 19, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro software v21.3. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
July 19, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
Learn to accelerate AI applications with just a few lines of code using Intel® Extension for PyTorch*, and then tune performance to take the highest advantage of advanced features in Intel hardware.
July 12, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to use the Intel® Quartus® Prime Pro Edition software and correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected through VMware* for labs. No setup is needed.
July 12 - 13, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
This class is an introduction to HDL and its use in programmable logic design, covering the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through VMware* for labs. No set up is needed.
July 12 - 13, 9:00 a.m.-1:30 p.m. Pacific Daylight Time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Closure–Lecture class. Use the Intel® Quartus® Prime Software to practice timing closure techniques. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
July 11, 9:00 a.m.-1:30 p.m. Central European Time (CET)
Learn techniques used by design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
July 10, 9:00 a.m.-1:30 p.m. Central European Time (CET)
Get an introduction to the new features of PyTorch* 2.0, which includes exploring the framework’s deep learning compiler technologies.
June 28, 2023, 4:00 p.m. Pacific daylight time (PDT)
The field of generative AI is rapidly advancing, bringing with it potential applications that could fundamentally alter the future of human-computer interactions and collaborations. This workshop delves into transformer models, including Stable Diffusions and Generative Pretrained Transformers (GPT), and explores how these models are optimized to run on Intel’s variety of hardware. We’ll also take a look at Jupyter* Notebook tutorials that you can run on your own machine, providing hands-on experience with these powerful tools.
June 28, 2023, 9:00 a.m.-10:00 a.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Analysis–Lecture class. Get a brief review of the SDC constraints learned in the previous class before starting the labs. You will use a remote computer connected through VMware*. No set up is needed.
June 27, 2023 9:00 a.m.-1:30 p.m. Central European Time (CET)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
June 26, 2023 9:00 a.m.-1:30 p.m. Central European Time (CET)
If complex math makes up the foundations of your applications and solutions, sign up for a session that’s focused on the power and performance delivered by oneMKL.
June 21, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool that is part of the Intel® Quartus® Prime Software. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
June, 21 2023 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and complex programmable logic devices (CPLD). You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
Jun 21, 2023 9:00 a.m.- Jun 22, 2023 1:30 p.m. Pacific daylight time (PDT)
Food and drinks! Let’s hang out after the day’s conference at our networking meetup.
Tuesday, June 20th, 2023, 7:00 p.m. - 9:00 p.m. Pacific daylight time (PDT)
This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. You will use a remote computer connected through VMware* for labs. No set up is needed.
Jun 20, 2023 9:00 a.m.-1:30 p.m. central European time (CET)
Learn about the final set of open source AI reference kits, purpose-built to help you overcome the challenges of AI acceleration along the development pipeline.
June 14, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn what an FPGA is and its basic features. Get a description of the development flow for an FPGA design. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
June 14, 2023 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This event helps familiarize developers with oneAPI tools and the programming environment through several hands-on training sessions. Bring your CUDA* code and port it to C++ with SYCL* and oneAPI.
June 14, 2023, 8:30 a.m. – 4:00 p.m. central daylight time (CDT)
This virtual community conference is focused on technical talks and workshops that highlight the capabilities of the oneAPI tools and motivate you to start building your own oneAPI projects.
June 13, 2023, 9:00 a.m.-5:00 p.m. central daylight time (CDT)
The Intel® oneAPI Toolkits are based on Data Parallel C++ (DPC++, a modern version of C++ and SYCL*) that allows developers to develop, optimize, and deploy algorithms for heterogenous compute platforms, and program FPGAs. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
June 13, 2023 9:00 a.m.-1:30 p.m. central European time (CET)
Advance your coding capabilities with efficient Python* techniques.
June 8, 2023, Pacific daylight time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Closure–Lecture class. Use the Intel® Quartus® Prime Software to practice timing closure techniques. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
June 8, 2023 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn about a modern C++ library used for task-based parallelism on CPUs.
June 7, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to create a design using Nios® V IP Suite in the Platform Designer for Intel® Quartus® Software. Program with software-building tools a development kit to use Nios® V processor. You will use a remote computer connected through VMware* for labs. No set up is needed.
June 7, 2023 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn techniques used by design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
June 7, 2023 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn how to use the Intel® Quartus® Prime Pro Edition software and correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected through VMware* for labs. No setup is needed.
June 5, 2023 9:00 a.m. - Jun 6, 2023 1:30 p.m. central European time (CET)
OpenVINO™ Toolkit's newest release, 2023.0, marks a significant milestone for its five-year anniversary. Hear rare insights from the past and present about the toolkit's evolution from the individual behind the product: Yury Gorbachev, Intel Fellow, OpenVINO Product Architecture. Get highlights of what’s new in the release including: More integrations (like TensorFlow* and PyTorch* front ends), expanded model support (such as Segment Anything, GPT-J, and YOLO v8)*, and gaining efficiencies on CPUs with thread scheduling.
May 31, 2023: 9:00 a.m.-10:00 a.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Analysis–Lecture class. Get a brief review of the SDC constraints learned in the previous class before starting the labs. You will use a remote computer connected through VMware*. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn how to implement and configure first-stage and second-stage bootloaders (based on U-Boot) and how to build and boot to Linux*. Understand the boot stages of Intel® SoC FPGAs. You will use a remote computer connected through VMware* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Advance your mastery of visualization techniques with this toolkit.
May 25, 2023, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn how next-generation hardware and software solutions interact for communication, I/O, and storage subsystems that are tied together to support HPC and data analytics at the systems level, and how to use them effectively.
May 25, 2023, 9:00 a.m.-6:00 p.m. central European time (CET)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Get an introduction to boosting model training and inference with very few code changes on the latest Intel® CPUs using Intel® Optimization for PyTorch* and Intel® Optimization for TensorFlow*.
May 24, 2023, 9:00 a.m. Pacific daylight time (PDT)
Enjoy the in-person experiences surrounding sessions, workshops, demos, labs, and training available at this summit in Boston, Massachusetts. Its keynotes, customer and partner stories, and topics and tracks are designed to help you make the most of hybrid cloud technology.
May 23-25, 2023, 8:00 a.m.-7:00 p.m. Eastern time (ET)
Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and complex programmable logic devices (CPLD). You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
9:00 a.m.-1:30 p.m. central European time (CET)
Intel is a sponsor for this event that features high-performance computing (HPC), machine learning, data analytics, and quantum computing. It’s in-person in Hamburg, Germany.
May 21-25, 2023, 8:00 a.m.-6:00 p.m. Central European time (CET)
Learn how to use the Intel® Quartus® Prime Pro Edition Software and correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected through VMware* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This premier North American event for open source developers, technologists, and community leaders is a gathering place for open source code and community contributors. Intel is a gold sponsor.
May 10-12, 2023, 9:00 a.m. Pacific daylight time (PDT), Los Angeles, California
This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. You will use a remote computer connected through VMware* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This class is a general introduction to the Verilog language and its use in programmable logic design. It covers the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through VMware* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. central European time (CET)
This class is a general introduction to the Verilog language and its use in programmable logic design. It covers the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through VMware* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn how to create a design using Nios® V IP Suite in the Platform Designer for Intel® Quartus® Software. Program with software-building tools a development kit to use Nios® V processor. You will use a remote computer connected through VMware* for labs. No set up is needed.
April 27, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
In this workshop, learn how to migrate code in C++ to SYCL for simple data analytics and machine learning workloads.
April 27, 2023, 3:00 p.m. to 5:00 p.m. India Standard Time (IST)
Optimize your neural networks (particularly your BERT models) on CPUs using Intel® Neural Compressor with a Transformer model showcase.
April 26, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool that is part of the Intel® Quartus® Prime Software. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
April 26, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and complex programmable logic devices (CPLD). You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
April 26, 2023, 9:00 a.m. - April 27, 2023, 1:30 p.m. Pacific daylight time (PDT)
SYCL* provides a powerful way to take advantage of the capabilities of CPUs and GPUs to drive simulations in a parallel and efficient manner. By using SYCL parallel-processing capabilities, you can accelerate the simulation of complex problems that would otherwise be computationally expensive or infeasible to solve. You will see it in a demo.
April 26, 2023, 5:00 p.m. – 7:00 p.m. Indian standard time (IST)
Learn what an FPGA is and its basic features. Get a description of the development flow for an FPGA design. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
April 24, 2023, 9:00 a.m.-1:30 p.m. Central European time (CET)
This workshop focuses on techniques you can use to gain maximum optimization when programming with oneDPL.
April 20, 2023, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Closure–Lecture class. Use the Intel® Quartus® Prime Software to practice timing closure techniques. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
April 20, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn how to deploy high-availability machine learning solutions on AWS* using Intel’s new cloud-optimization module for Kubernetes*.
April 19. 2023, 9:00 a.m. Pacific daylight time (PDT)
This class teaches the techniques used by design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
April 19, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This workshop gives a basic understanding of Intel® oneAPI Deep Neural Network Library (oneDNN) and Intel® oneAPI Data Analytics Library (oneDAL), and includes a quick hands-on session to offer participants experience in implementing and optimizing neural networks using these libraries.
April 19, 2023, 5:00 p.m. to 7:00 p.m. India Standard Time (IST)
The Cloud Native Computing Foundation (CNCF) flagship conference gathers adopters and technologists from leading open source and cloud native communities in Amsterdam, the Netherlands. Join our CNCF graduated and incubating projects as the community gathers for four days to further the education and advancement of cloud native computing.
April 18-21, 2023
This workshop presents advanced concepts in SYCL* programming.
April 13, 2023, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Intel® FPGA Timing Analysis–Lecture class. Get a brief review of the SDC learned in the previous class before starting the labs. You will use a remote computer connected through VMWare* Lab Platform for labs. No set up is needed.
April 13, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Get a comprehensive walk-through of Intel’s one-stop portal for migrating CUDA* code to C++ with SYCL*, which includes step-by-step tutorials, tools, and code samples.
April 12, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
April 12, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn the essential methods and tools for accelerating math-processing computations and offloading application tasks on Intel® GPUs.
April 5, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn what an FPGA is and its basic features. Get a description of the development flow for an FPGA design. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
April 5, 2023, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Advance your understanding of SYCL* concepts in this live workshop conducted on Intel® Developer Cloud, which provides access to hands-on coding.
April 4, 2023, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Gain a solid foundation and working understanding of the Intel® oneAPI tools and Intel® Developer Cloud.
March 30, 2023, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn how to speed up the performance and efficiency of your AI workloads on Intel’s newest CPUs and GPUs using Intel® Advanced Matrix Extensions (Intel® AMX) and Intel® Xe Matrix Extensions (Intel® XMX).
March 29, 2023, 9:00 a.m. Pacific daylight time (PDT)
Learn how to use the Intel® Quartus® Prime Pro Edition software and correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected through VMware* for labs. No set up is needed. March 29-30, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn how to implement and configure the first-stage and second-stage bootloaders (based on U-Boot), build and boot to Linux*, and the boot stages of Intel® SoC FPGAs. You will use a remote computer connected through VMware* for labs. No set up is needed. March 27, 9:00 a.m.-1:30 p.m. Central European time (CET)
9:00 a.m.-1:30 p.m. Central European time (CET)
Create a design using the Nios® V IP Suite in the platform designer for Intel® Quartus® software. With software-building tools, program a development kit to use a Nios V processor. You will use a remote computer connected through VMware* for labs. No set up is needed. March 16, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
The latest set of 22 trained, open source AI reference kits are here, purpose-built to help you overcome the challenges of AI acceleration along the development pipeline.
March 15, 2023, 9:00 a.m. Pacific daylight time (PDT)
This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. You will use a remote computer connected through VMware* for labs. No set up is needed. March 15, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
9:00 a.m.-1:30 p.m. Pacific time (PT)
Strengthen your AI skills at this live virtual workshop.
March 14, 2023, 9:00 a.m.-11:30 a.m. Pacific daylight time (PDT)
Get a general introduction to the Verilog language and its use in programmable logic design. The class covers the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through VMware* for labs. No set up is needed. March 8-9, 9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn to implement and configure first-stage and second-stage bootloaders (based on U-boot), and how to build and boot them to Linux*. Learn the boot stages of each Intel® SoC FPGA. You will use a remote computer connected through Webex* for labs.
March 1, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Deepen your understanding of heterogeneous C++ programming so you can more effectively create and deploy multivendor applications.
February 28, 2023, 9:00 a.m. Pacific standard time (PST)
This workshop is a follow-on to the Intel® FPGA Timing Closure—Lecture class. Most of the workshop will be spent practicing timing closure techniques with the Intel® Quartus® Prime Software. You will use a remote computer connected through the VMware* Lab Platform for labs. No set up is needed.
February 23, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Learn the techniques used by design specialists to close timing on designs that exceed the limits of performance. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
February 22, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Get an introduction to the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
February 21, 2023, 10:00 a.m. - 2:30 p.m. Central European Time (CET).
Get best practices from Intel and Hugging Face* for optimizing multi-node, distributed transformer model training and inference on 4th gen Intel® Xeon® processors.
February 15, 2023, 9:00 a.m. Pacific standard time (PST)
Tailor your approach to developing efficient AI solutions with accelerated machine learning.
February 9, 2023, 9:00 a.m.-11:00 a.m. Pacific standard time (PST)
Learn efficient coding techniques for writing synthesizable Verilog HDL for Intel® FPGAs and CPLDs. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
February 8-9, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Learn how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool, a part of the Intel Quartus® Prime software. You will use a remote computer connected through Webex* for labs. No set up is needed.
February 6, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
This workshop is a follow-on to the Intel® FPGA Timing Analysis—Lecture class. Before starting the labs, get a brief review of the SDC constraints learned in the previous class. You will use a remote computer connected through Webex* for labs. No set up is needed.
February 2, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Learn how to constrain and analyze a timing design using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Webex* for labs. No set up is needed.
February 1, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Learn about the future of this compiler, including how it opens up the world of GPU offloading and programming on the latest discrete Intel® processors.
February 1, 2023, 9:00 a.m. Pacific standard time (PST)
Stretch your coding capabilities with advanced Python* techniques.
January 26, 2023, 9:00 a.m.-11:00 a.m. Pacific standard time (PST)
Learn about an FPGA, its basic features, and the development flow for its design. You will use a remote computer connected through VMware* Lab Platform for labs. No set up is needed.
January 25, 2023, 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Learn how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool (a part of the Intel® Quartus® Prime Software). You will use a remote computer connected through Webex* for labs. No set up is needed.
January 25, 2023., 9:00 a.m. - 1:30 p.m. Pacific standard time (PST)
Sign up to learn how the growing collection of open source reference kits for Intel® AI can kick-start an increasing array of AI solutions, whether you’re a small shop or a global organization.
Start on Building Performant AI Solutions Quickly
Wednesday, January 25, 2023, 9:00 a.m. Pacific standard time (PST)
This workshop is a follow-on to the Intel® FPGA Timing Closure—Lecture class. Most of the workshop will be spent practicing timing closure techniques with the Intel® Quartus® Prime Software. You will use a remote computer connected through the VMware* Lab Platform for labs. No set up is needed.
January 24, 2023, 10:00 a.m. - 2:30 p.m. Central European Time (CET)
Learn the techniques used by design specialists to close timing on designs that exceed the limits of performance. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
January 23, 2023, 10:00 a.m. - 2:30 p.m. Central European Time (CET)
Learn how to use this software and get a general flow of an FPGA design process. You will use a remote computer connected through VMware* Lab Platform for labs.
January 18, 2023 - January 19, 2023, 9:00 a.m. - 1:30 p.m. Pacific Standard Time (PST)
Learn how the latest Intel optimizations extend stock PyTorch on Intel hardware, including the Intel® Xeon® CPU Max Series (formerly code named Sapphire Rapids) and Intel® Data Center GPU Max Series (formerly code named Ponte Vecchio).
Wednesday, January 18, 2023, 9:00 a.m. Pacific standard time (PST)
Get a general introduction to the Verilog HDL and its use in programmable logic design, which covers the basic constructs used in simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.
January 11, 2023 - January 12, 2023, 9:00 a.m. - 1:30 p.m. Pacific Standard Time (PST)
This workshop is a follow-on to the Intel® FPGA Timing Analysis—Lecture class. Before starting the labs, get a brief review of the SDC constraints learned in the previous class. You will use a remote computer connected through the VMware* Lab Platform for labs. No set up is needed.
January 10, 2023, 10:00 a.m. - 2:30 p.m. Central European Time (CET)
Learn how to constrain and analyze a timing design using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Webex* for labs. No set up is needed.
January 9, 2023, 10:00 a.m. - 2:30 p.m. Central European Time (CET)
Learn how to boost Python* by using NumPy, SciPy, and pandas that are available through the Intel® AI Analytics Toolkit. Achieve performance increases of up to 100 times and higher.
December 15, 2022, 9:00 a.m.-11:00 a.m. Pacific standard time (PST)
This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime software. You will use a remote computer connected through Webex for labs. No setup is needed.
December 14, 9:00 a.m.-1:30 p.m. Pacific time (PT)
You will learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and CPLDs. You will use a remote computer connected through VLP for labs. No set up is needed.
December 14-15, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn how the latest Intel® optimizations extend stock TensorFlow*, delivering numerous machine learning performance boosts on Intel® CPUs and discrete GPUs.
December 14, 2022, 9:00 a.m. Pacific standard time (PST)
Speed up deep learning workload performance on Intel® CPUs and GPUs using Model Zoo optimized inference applications and the Intel® Extension for TensorFlow*, and then analyze and debug the results.
December 14, 2022, 5:00 p.m. Indian standard time (IST)
This workshop examines advanced concepts in SYCL* programming that use buffers and accessors for heterogeneous computing.
December 8, 2022, 9:00 a.m. - 11:00 a.m. Pacific standard time (PST)
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. You will use a remote computer connected through Webex for labs. No setup is needed.
December 7 - 8, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Organizations that focus strongly on performance have adopted the programming language Julia*. Adherents include NASA*, Climate Modeling Alliance, and CERN. In this virtual workshop, gain a solid introduction to Julia from Professor Alan Edelman. His presentation focuses on a sharper understanding of computational thinking and scientific computing.
December 2, 2022, 9:00 a.m. - 11:00 a.m. Pacific standard time (PST)
This workshop is a follow on to the Intel® FPGA Timing Closure: Lecture class. Your time during this workshop will mostly be spent using the Intel® Quartus® Prime Software to practice timing closure techniques. You will use a remote computer connected through VLP for labs. No setup is needed.
December 1, 9:00 a.m.-1:30 p.m. Pacific time (PT)
The 2023 release of Intel oneAPI will be available soon. Get an advance peek at what’s new plus engage in a live Q&A with Intel® software experts about all things oneAPI.
November 30, 2022, 9:00 a.m. Pacific standard time (PST)
This class will teach you how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool, part of the Intel Quartus® Prime software. You will use a remote computer connected through Webex* for labs. No set up is needed.
November 30, 9:00 a.m.-1:30 p.m. Pacific time (PT)
This class teaches the techniques used by design specialists to close timing on designs that “push the envelope” of performance. You will use a remote computer connected through Teams. No setup is needed.
November 30, 9:00 a.m.-1:30 p.m. Pacific time (PT)
This innovative workshop guides you through the AI techniques to create a likelihood map for discovering dinosaur bones in different locations. Explore machine learning algorithms powered by Intel® oneAPI software, including Intel® Extension for Scikit-learn*, NumPy, and Intel® Distribution of OpenVINO™ toolkit.
November 29, 2022, 9:00 a.m.-11:00 a.m. Pacific standard time (PST)
You will then learn to implement and configure the first-stage and second-stage bootloaders (based on U-Boot), and how to build and boot to the Linux* OS. You will learn the boot stages of each SoC FPGA family. You will use a remote computer connected through VLP for labs. November 29, 10:00 a.m.-2:30 p.m. Central European Time (CET)
This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime software. You will use a remote computer connected through Webex for labs. No setup is needed. November 17, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn how to use Python* parallel programming for accelerated performance on multiple hardware acceleration devices such as GPUs and FPGAs.
November 16, 2022 9:00 a.m. Pacific standard time (PST)
You will learn how to use the Intel® Quartus® Prime Pro Edition software & correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected through VLP for labs. November 16-17, 9:00 a.m.-1:30 p.m. Pacific time (PT)
You will then learn to implement and configure the first-stage and second-stage bootloaders (based on U-Boot), and how to build and boot to the Linux* OS. You will learn the boot stages of each SoC FPGA family. You will use a remote computer connected through VLP for labs. November 16, 9:00 a.m.-1:30 p.m. Pacific time (PT)
This is an multiphased, open event that runs from November 15, 2022, through February 19, 2023.
- Phase 1: Idea Submission (November 15, 2022, 6:00 p.m. to January 15, 2023, 11:59 p.m. Indian standard time (IST)
- Phase 2: Prototype Submission (February 3, 2023, 6:00 p.m. to February 19, 2023, 11:59 p.m. (IST)
Join on your own, create a team, or join another team (maximum of five members per team). Sharpen your development skills and showcase your work. Learn with Intel experts on machine learning, computer vision, and oneAPI open social innovation. You also have a chance to win fantastic prizes.
You will learn how to use the Intel® Quartus® Prime Pro Edition software & correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected through VLP for labs. November 14-15, 10:00 a.m.-2:30 p.m. Central European Time (CET)
Learn about open source AI reference kits that are purpose-built to help you overcome the challenges of AI acceleration along the development pipeline.
November 9, 2022, 9:00 a.m. Pacific daylight time (PDT)
You will learn what an FPGA is, and the basics features of an FPGA. During class, the development flow for an FPGA design will be described. You will use a remote computer connected through Webex* for labs. No set up is needed. November 9, 9:00 a.m.-1:30 p.m. Pacific time (PT)
You will learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and CPLDs. You will use a remote computer connected through VLP for labs. No set up is needed. November 9-10, 9:00 a.m.-1:30 p.m. Pacific time (PT)
You will learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and CPLDs. You will use a remote computer connected through VLP for labs. No set up is needed. November 7-8, 10:00 a.m.-2:30 p.m. Central European Time (CET)
This workshop is a follow on to the Intel FPGA Timing Analysis – Lecture class. There will be a brief review of the SDC constraints learned in the previous class before starting the labs. You will use a remote computer connected through VM for labs. No setup is needed. November 3, 9:00 a.m.-1:30 p.m. Pacific time (PT)
TensorFlow* developers can learn strategies for identifying and fixing the parts of compute-intensive AI workloads that cause performance bottlenecks.
November 2, 2022, 9:00 a.m. Pacific daylight time (PDT)
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. You will use a remote computer connected through Webex for labs. No setup is needed. November 2-3, 9:00 a.m.-1:30 p.m. Pacific time (PT)
You will learn how to constrain & analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro software v. 21.3. You will use a remote computer connected through Webex for labs. No setup is needed. November 2, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Get near-native speed from your AI and data science workloads—even in accelerated computing environments—with minimal code changes.
October 26, 2022, 9:00 a.m., Pacific daylight time (PDT)
Join a virtual conference that's focused on AI, oneAPI, and SYCL* for accelerated computing across xPU architectures. Learn from leading industry and academia speakers who innovate new oneAPI solutions for cross-platform, multivendor architecture.
October 26-27, 2022 2:00 p.m. - 5:00 p.m. Japan standard time (JST)
Learn how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool (part of the Intel® Quartus® Prime Software). You will use a remote computer connected through Webex* for labs. No set up is needed.
10:00 a.m.-2:30 p.m. Central European time (CET)
Speed up photorealistic rendering with Intel® Embree, an open source kernel framework for efficient and professional ray tracing on CPUs.
October 19, 2022, 9:00 a.m.-10:30 a.m. Pacific daylight time (PDT)
Get an overview of scikit-learn* essentials for machine learning. In the Intel® Developer Cloud, practice using the Intel® AI Analytics Toolkit. You'll dramatically accelerate key machine learning algorithms that include principal component analysis (PCA), K-nearest neighbors (KNN), linear regression, support vector classification (SVC).
October 18, 2022, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Timing Analysis for Intel® FPGA– Lecture class. There will be a brief review of the SDC constraints learned in the previous class before starting the labs. You will use a remote computer connected through Webex* for labs. No set up is needed.
10:00 a.m.-2:30 p.m. Central European time (CET)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Webex* for labs. No set up is needed.
10:00 a.m.-2:30 p.m. Central European time (CET)
This workshop is a follow-on to the Timing Closure for Intel® FPGA—Lecture class. Your time will mostly be spent using the Intel® Quartus® Prime Software to practice timing closure techniques. You will use a remote computer connected through VLP for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PT)
SYCL* atomic operations and device-specific local memory share the focus in this hands-on workshop. Both are useful for kernel programming when offloading operations to GPU devices.
October 13, 2022, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn techniques used by design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
The free Intel® VTune™ Profiler (included in the Intel® oneAPI Base Toolkit) is the key to eliminating performance bottlenecks that can bog down applications and frustrate developers. In this live virtual workshop, unlock the mysteries of successful performance profiling to better understand the techniques and discover the most effective ways to optimize applications.
October 11, 2022, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
This workshop is a follow-on to the Timing Analysis for Intel® FPGA– Lecture class. There will be a brief review of the SDC constraints learned in the previous class before starting the labs. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn the tools and a methodology to quickly and efficiently profile systems for in-depth power and thermal behavior.
October 5, 2022, 9:00 a.m.-10:30 a.m. Pacific daylight time (PDT)
Learn about an FPGA and its basic features, and the development flow for an FPGA design. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This course introduces the Signal Tap embedded logic analyzer, one of many debug tools included in the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
10:00 a.m.-2:30 p.m. Central European time (CET)
Get an introduction to the Numba* data-parallel extension (numba-dpex) and examples of writing data-parallel code inside @numba.jit decorated and @kernel decorator functions to offload them to a SYCL* device.
September 29, 2022, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Ask an expert about the Arm* Development Studio for Intel® SoC FPGA, an embedded C/C++ development toolchain designed for Arm-based SoCs. Come and get answers to questions or interact with other like-minded designers who are working on embedded development with Arm SoCs.
September 29, 9:00 a.m., Pacific standard time (PST)
Learn efficient coding techniques for writing synthesizable Verilog HDL for Intel® FPGAs and CPLDs. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Intel® VTune™ Profiler was created to manage full-spectrum evaluation, turning raw data into answers for HPC, cloud, IoT, media, storage, and more. In this session, technical consulting engineer James Tullos unpacks the details.
September 28, 2022, 9:00 a.m. Pacific daylight time (PDT)
Develop software for and design with Intel® FPGA SoC FPGAs using the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
10:00 a.m.-2:30 p.m. Central European time (CET)
Develop software for and design with Intel® FPGA SoC FPGAs using the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Get an introduction to using the compiler for cross-architecture development and deployment. Participate in hands-on demonstrations to get started quickly across CPUs and GPUs.
September 21, 2022, 9:00 a.m. Pacific daylight time (PDT)
This oneAPI solution delivers a unified programming model to simplify development across diverse architectures. When combined with SYCL*, the Intel® oneAPI DPC++ Library (oneDPL) provides high-productivity APIs to developers.
September 20, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
This is a follow-on workshop to the lecture on Intel® FPGA timing closure where you will use the Intel® Quartus® Prime Software to practice timing closure techniques. You will use a remote computer connected through the VMware* Learning platform for labs. No set up is needed.
9/20/2022
10:00 a.m. - 2:30 p.m. Central European time (CET)
Learn techniques used by design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Microsoft Teams*. No set up is needed.
9/19/2022
10:00 a.m. - 2:30 p.m. Central European time (CET)
Get an introduction to the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This event is for C++ and GPU programmers, AI developers, researchers, or data scientists who develop applications in HPC and AI. Register today.
September 15, 2022, 9:00 a.m.-6:00 p.m. Indian standard time (IST)
Quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool, part of the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn how the Intel® DPC++ Compatibility Tool can port CUDA* to DPC++/SYCL* code in a one-time migration activity that includes kernels and library API calls.
September 14, 2022, 9:00 a.m. Pacific daylight time (PDT)
Understand why performance, portability, and productivity are important for HPC development. Get hands-on practice for methods to achieve performance-portable code that can run across different CPUs and GPUs available on the Intel® DevCloud.
September 13, 2022, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Get an introduction to Verilog HDL, its use in programmable logic design, and basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.
10:00 a.m.-2:30 p.m. Central European time (CET)
Get an introduction to Verilog HDL, its use in programmable logic design, and basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Migrate your C/C++ code to SYCL* with oneAPI so that the same code not only targets FPGAs, but also GPUs and CPUs.
Wednesday, August 31, 2022 | 9:00 a.m., Pacific daylight time (PDT)
Learn how to use the Intel® Quartus® Prime Pro Edition Software within a general FPGA design process. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Get an introduction to the Signal Tap embedded logic analyzer, one of the many debug tools included in the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
10:00 a.m.-2:30 p.m. Central European time (CET)
This workshop is a follow-on to the Intel® FPGA Timing Analysis class. Before starting the labs, you'll get a brief review of the Synopsis design constraints (SDC) learned in the previous class. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Java* developers and performance engineers can overcome the challenges of analyzing and optimizing their cloud workloads (public, private, or both).
Wednesday, August 24, 2022 | 9:00 a.m., Pacific daylight time (PDT)
Constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
Learn about an FPGA, its basic features, and the development flow for an FPGA design. You will use a remote computer connected through Webex* for labs. No set up is needed.
10:00 a.m.-2:30 p.m. Central European time (CET)
Advance your understanding of SYCL concepts in this live workshop conducted on Intel® DevCloud, providing access to hands-on coding. The workshop will highlight techniques for achieving efficient results on modern architectures with diverse hardware systems.
August 18, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn the power of drop-in acceleration for popular frameworks such as TensorFlow and pandas so you can focus on improving your models and gaining insights throughout the AI cycle.
August 17, 2022
9:00 a.m. Pacific daylight time (PDT)
Learn about an FPGA, its basic features, and the development flow for an FPGA design. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
This workshop—hosted on Intel® DevCloud—shows how these resources can improve predictive modeling implementations. Start at a basic decision tree and advance to techniques that balance the tradeoffs of speed and accuracy.
August 16, 2022, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool, part of the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
9:00 a.m.-1:30 p.m. Pacific daylight time (PDT)
The Intel® AI Analytics Toolkit (AI Kit) lets you supercharge Python* performance using NumPy, SciPy, and pandas.
Using Intel® DevCloud, the workshop explores several NumPy aggregations, universal functions, broadcasting, and other techniques made available by the AI Kit and oneAPI libraries.
August 11, 2022, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Overcome the challenges of AI acceleration along the development pipeline by using a new set of reference kits for problems across healthcare, manufacturing, retail, and more.
August 10
9:00 a.m. Pacific daylight time (PDT)
Ignite performance of common Python and pandas constructs by exploiting the capabilities of NumPy, SciPy, and pandas, powered by oneAPI.
July 27, 2022
9:00 a.m. Pacific daylight time (PDT)
Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and CPLDs. You will use a remote computer connected through Webex* for labs. No set up is needed.
July 27-28, 2022
9:00 a.m.-1:30 p.m. (PDT)
Learn about the Signal Tap logic analyzer in Intel® Quartus® Prime Software. Bring your questions to ask the experts about FPGA design debugging during the interactive session.
July 27
9:00 a.m. - 10:00 a.m. Pacific daylight time (PDT)
As FPGA designs become more complex, a larger part of development time is spent verifying designs. You will use a remote computer connected through Webex* for labs. No set up is needed.
July 26, 2022
9:00 a.m.-1:30 p.m. (PDT)
Gain a solid foundation and working understanding of the Intel® oneAPI tools and Intel® DevCloud. The workshop introduces the underlying structures that make oneAPI an invaluable tool for streamlining development across diverse architectures.
July 26, 9:00 a.m.-11:00 a.m. Pacific daylight time (PDT)
Learn how to perform reduction operations in oneAPI using SYCL or oneDPL, and learn the advantages of each approach.
July 13, 2022
9:00 a.m. Pacific daylight time (PDT)
Get a general introduction to the Verilog language and its use in programmable logic design. The class covers the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.
July 13-14, 2022
9:00 a.m.-1:30 p.m. (PDT)
Join us for this live (and free) virtual event focused on the latest AI technology advancements that can start or advance your development career.
July 12, 2022
9:00 a.m. - 5:00 p.m. Pacific daylight time (PDT)
Get a general introduction to the Verilog language and its use in programmable logic design. The class covers the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.
July 11-13, 2022
10:00 a.m.-2:30 p.m. (CET)
Learn the basics of this tool: The standard interfaces it supports, how to create new or add to existing HDL designs to implement these interfaces, and how to integrate custom components into the tool. You will use a remote computer connected through Webex* for labs. No set up is needed.
July 7, 2022
9:00 a.m.-1:30 p.m. (PDT)
Learn how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool (part of the Intel® Quartus® Prime Software). You will use a remote computer connected through Webex* for labs. No set up is needed.
July 6, 2022
9:00 a.m.-1:30 p.m. (PDT)
Learn how to use the Intel® Quartus® Prime Pro Edition Software. Correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected through Webex* for labs. No set up is needed.
July 6-7, 2022
9:00 a.m.-1:30 p.m. (PDT)
Get hands-on experience using the Intel® AI Analytics Toolkit to explore predictive modeling techniques based on decision trees. Take popular decision-tree algorithms (used for regression and classification tasks) and address the challenge of handling training when data sizes increase.
June 30, 9:00 a.m.-11:00 a.m. (PDT)
This class teaches the techniques used by FPGA design specialists to close timing on designs that surpass the normal limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 29-30, 9:00 a.m.-1:30 p.m. (PDT)
Take a tour of a new data-science workstation solution that's purpose-built to shrink the time data practitioners spend on model development and optimization.
Wednesday, June 29, 9:00 a.m.-10:00 a.m. (PDT)
Learn and practice advanced concepts and features of Data Parallel C++ (DPC++) using live sample code on Intel® DevCloud.
June 24, 2022
3:00 p.m. - 5:00 p.m. India standard time (IST)
This workshop is a follow on to the Intel® FPGA Timing Analysis lecture. It briefly reviews the SDC constraints learned in the previous class before starting the labs. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 23, 9:00 a.m.-1:30 p.m. (PDT)
Venture deeper into effective methods to accelerate machine-learning workloads. Uncover new way to harness the K-means and GPairs algorithms.
June 23, 9:00 a.m. (PDT)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 22, 9:00 a.m.-1:30 p.m. (PDT)
Learn how to use the Intel® Quartus® Prime Pro Edition Software and correlate it to the general flow of an FPGA design process. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 22-23, 9:00 a.m.-1:30 p.m. (PDT)
Learn how to use the Intel® Gaussian & Neural Accelerator (integrated with Intel® Core™ processors) to optimize AI noise cancellation while increasing battery life and decreasing CPU use.
Wednesday, June 22, 9:00 a.m.-10:00 a.m. (PDT)
Use the Intel® oneAPI AI Analytics Toolkit to discover efficient methods for implementing these algorithms.
June 21, 9:00 a.m. (PDT)
This class teaches the techniques FPGA design specialists use to close timing on designs that surpass the normal limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 20-21, 10:00 a.m.-2:30 p.m. (CET)
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 15-16, 9:00 a.m.-1:30 p.m. (PDT)
Designing code for GPU offload can be a struggle when it comes to ensuring the ported application is tapping into all of that hardware power. Sign up to learn how one tool can set you up for fast success.
Wednesday, June 15, 2022, 9:00 a.m. (PDT)
This workshop is a follow on to the Intel® FPGA Timing Analysis lecture. It briefly reviews the SDC constraints learned in the previous class before starting the labs. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 14, 10:00 a.m.-2:30 p.m. (CET)
OpenVINO™ DevCon is a day-long virtual developer conference. Version 2022.1 of the OpenVINO™ toolkit marks a major milestone with new speech capabilities, automatic hardware optimizations, and a revamped API. Join us for a free day of in-depth information, ask me anything (AMA), and an AI challenge that introduces you to new capabilities and hands-on experience with the toolkit.
June 13, 8:00 a.m.-4:30 p.m. (PDT)
Learn how to constrain and analyze a design for timing using the Timing Analyzer in Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 13, 10:00 a.m.-2:30 p.m. (CET)
As FPGA designs become more complex, a larger part of development time is spent verifying designs. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 8-9, 9:00 a.m.-1:30 p.m. (PDT)
Learn how to design with an Intel® FPGA system-on-a-chip (SoC) using the Intel® Quartus® Prime Software and how to develop software for these devices. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 8-9, 9:00 a.m.-1:30 p.m. (PDT)
Find out how using low-precision techniques with Intel® Neural Compressor not only speed up model post-training but also preserve accuracy and performance.
Wednesday, June 8, 2022, 9:00 a.m. (PDT)
Learn the basics for the standard interfaces supported in Platform Designer, how to create new or add to existing hardware description language (HDL) designs to implement these interfaces, and how to integrate your custom components into the tool. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 2, 9:00 a.m.-1:30 p.m. (PDT)
Learn efficient coding techniques for writing synthesizable code in Verilog for Intel® FPGAs and complex programmable logic devices (CPLD). You will use a remote computer connected through Webex* for labs. No set up is needed.
June 1-2, 9:00 a.m.-1:30 p.m. (PDT)
This class teaches you how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool, part of the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
June 1, 9:00 a.m.-1:30 p.m. (PDT)
Attend a day of hands-on tutorials, tech talks, and a panel focused on high-performance computing (HPC) and AI workloads developed on oneAPI.
Friday, May 27, 9:00 a.m.-6:00 p.m. (CET)
Learn why performance, portability, and productivity are important for high-performance computing (HPC) development. Get hands-on practice for methods to achieve performance-portable code that can run across different CPUs and GPUs on the Intel® DevCloud.
Thursday, May 26, 9:00 a.m.-11:00 a.m. (PDT)
This class teaches the techniques FPGA design specialists use to close timing on designs that surpass the normal limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed.
May 25-26, 9:00 a.m.-1:30 p.m. (PDT)
Using pandas APIs for data analysis works great as long as the dataset is relatively small. But that’s often not the case—today’s AI datasets are several gigabytes or larger, which isn't ideal for speed and scale. Find out how Modin* solves these issues.
Wednesday, May 25, 2022, 9:00 a.m. (PDT)
Get an introduction to Intel® Extension for PyTorch* (part of the Intel® Optimization for PyTorch*). It extends stock PyTorch with optimizations for an extra performance boost on Intel® architecture.
Tuesday, May 24, 9:00 a.m.-11:00 a.m. (PDT)
Learn how to use the Intel® Quartus® Prime Pro Edition Software to develop an FPGA from its initial design to programming the device. You will use a remote computer connected through Webex* for labs. No set up is needed.
May 23-24, 9:00 a.m.-1:30 p.m. (PDT)
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.
May 23-24, 10:00 a.m.-2:30 p.m. (CET)
This workshop is a follow up to the lecture for Intel® FPGA timing analysis. There will be a brief review of the SDC constraints learned in the previous class before starting the labs. You will use a remote computer connected through Webex* for labs. No set up is needed.
May 19, 9:00 a.m.-1:30 p.m. (PDT)
You will learn how to constrain and analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software v21.3. You will use a remote computer connected through Webex* for labs. No set up is needed.
May 18, 9:00 a.m.-1:30 p.m. (PDT)
When scaling your applications for optimal performance on multiple cores or architectures, you’ll likely hit some roadblocks. This session demonstrates how to find and remove them.
Wednesday, May 18, 2022, 9:00 a.m. (PDT)
Learn how to use the Intel® Quartus® Prime Pro Edition Software to develop an FPGA from its initial design to programming the device. You will use a remote computer connected through Webex* for labs. No set up is needed.
May 16-17, 10:00 a.m.-2:30 p.m. (CET)
The workshop will cover:
- Overview of the Intel® oneAPI AI Analytics Toolkit
- Introduction to Intel® Optimization for TensorFlow*
- Optimizations from Intel for TensorFlow
- Performance boost numbers
- Hands-on demonstration to showcase the use and performance boost on Intel® DevCloud
May 13, 2022
3:00 p.m.-5:00 p.m. (IST)
Learn how to speed up deep-learning inferencing with the Intel® Neural Compressor. Get hands-on training with Intel® DevCloud. Discover the Intel® oneAPI AI Analytics Toolkit. Learn about Intel® Optimization for TensorFlow*.
May 13, 2022
3:00 p.m. - 5:00 p.m. Indian Standard time (IST)
Debug anywhere and on any device. Learn how to transform challenges to efficiency when debugging parallel and threaded oneAPI applications running concurrently on CPUs and GPUs.
May 11, 2022
9:00 a.m. (PDT)
Hear from customers, partners, and Intel leaders about the latest awe-inspiring technology advancements being made to help solve your most pressing business challenges.
8:00 a.m. -5:00 p.m.America/Los Angeles - PST/PDT
This class will teach you the basics creating custom components. You’ll learn the standard interfaces supported in Platform Designer, how to create new or add to existing Hardware Description Language (HDL) designs to implement these interfaces, and how to integrate your custom components into the tool. You will use a remote computer connected through Webex* for labs. No set up is needed.
May 5, 9:00 a.m.-1:30 p.m. (PDT)
Learn how to speed up many scikit-learn* machine-learning algorithms on CPUs and GPUs with only a few lines of Python* code.
May 4, 2022
9:00 a.m. (PDT)
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.
May 4-5, 9:00 a.m.-1:30 p.m. (PDT)
This class will teach you how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool that is part of the Intel® Quartus® Prime Software. You will use a remote computer connected through Webex* for labs. No set up is needed.
May 4, 9:00 a.m.-1:30 p.m. (PDT)
This final part of a two-part workshop series demonstrates how to speed up your key machine learning algorithms that rely on scikit-learn, and get faster results without specialized hardware.
Learn more about extending the capability using a compute follows data method of leveraging Intel® Extension for Scikit-learn* on current and upcoming Intel® GPUs.
April 28, 9:00 a.m.-11:00 a.m. PST
Learn how to use the Intel® Quartus® Prime Pro Edition Software to develop an FPGA and correlate these steps to tools from other vendors.
April 27-28
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
Learn advanced and efficient coding techniques for writing synthesizable Verilog code for Intel® FPGAs and complex programmable logic devices (CPLD). This course uses a remote computer connected through Webex* for labs. No setup is needed.
April 27-28
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
Using Intel® Extension for Scikit-learn* can significantly speed up machine learning performance. Get hands-on practice on our Intel® DevCloud during this workshop. Learn how to use the Intel® oneAPI AI Analytics Toolkit (AI Kit) to dramatically accelerate key machine learning algorithms, such as principal component analysis (PCA), k-nearest neighbor (KNN), linear regression, support-vector classification (SVC) and more.
April 26, 9:00 a.m. - 11:00 a.m. PST
Learn about debugging tools used for Intel® FPGAs and why more time is needed to verify complex FPGA designs.
April 25-26
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
In a bid to accelerate Python* for data science and machine learning, Intel is collaborating with Analytics India Magazine (a certified oneAPI technology partner) to bring you this oneAPI AI Analytics workshop.
April 22, 2022, 3:00 p.m.-5:00 p.m. (IST)
Learn the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. The course uses a remote computer connected through Webex* for labs. No setup is needed.
April 20-21
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
Gradient boosting is one of the most powerful techniques for building predictive models but handling large data sizes and memory can be challenging. Find out how Intel®-optimized XGBoost removes these obstacles.
April 13, 2022
9:00 a.m. (PDT)
Attend this 40-minute lecture and three-hour instructor-led course to learn how FPGAs work. Explore the associated design flow using Intel® Quartus® Prime Software.
April 11
8:00 a.m.-12:00 p.m. PDT (Pacific daylight time)
Learn the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. The course uses a remote computer connected through Webex* for labs. No setup is needed.
April 11-12
10:00 a.m.-2:30 p.m. CET (Central European time)
Get an introduction to the Verilog language and how to use it in programmable logic design. Explore the basic constructs used in simulation and synthesis environments. This course uses a remote computer connected through Webex* for labs. No setup is needed.
April 6-7
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
Learn to quickly build designs for Intel® FPGAs using the system-level integration tool, Platform Designer, which is part of Intel® Quartus® Prime Software. Increase your proficiency with the software and learn how to integrate off-the-shelf intellectual property and custom logic into a system.
April 6-7
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer feature in Intel® Quartus® Prime Pro Edition Software. This course uses a remote computer connected through Webex* for labs. No setup is needed.
April 4-5
10:00 a.m.-2:30 p.m. CET (Central European time)
Learn and practice the advanced concepts and features of Data Parallel C++ (DPC++) with live sample code on Intel® DevCloud. At the end of this workshop, you will be able to efficiently write SYCL code for heterogenous computing.
March 21, 2022
9:00 a.m. - 10:30 a.m. Pacific daylight time (PDT)
Speed up deep-learning workload performance on Intel® CPUs and GPUs using the Model Zoo optimized inference applications and the Intel® Extension for TensorFlow*, and then analyze and debug the results.
Learn about debugging tools used for Intel® FPGAs and why more time is needed to verify complex FPGA designs.
March 30-31
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer feature in Intel® Quartus® Prime Pro Edition Software. This course uses a remote computer connected through Webex* for labs. No setup is needed.
March 30-31
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
Get help from an expert on the Platform Designer tool in the Intel® Quartus® Prime Software. During this interactive session, you can get answers to questions or interact with other like-minded designers who are using Platform Designer.
March 30, 2022
9:30 a.m.-10:30 a.m. (IST)
oneAPI is a productive, smart path to freedom for accelerated computing, delivering a unified programming model for development across diverse architectures. If you are a developer with a foundational knowledge of C or C++, FPGA and GPU Programming, this workshop is for you.
March 29, 2022
9:00 a.m. - 10:30 a.m. Pacific daylight time (PDT)
Get help from an expert on the Platform Designer tool in the Intel® Quartus® Prime Software. During this interactive session, you can get answers to questions or interact with other like-minded designers who are using Platform Designer.
March 29, 2022
9:00 a.m.-10:00 a.m. (PDT)
Intel and Analytics India Magazine are presenting a workshop for the Intel® oneAPI AI Analytics Toolkit. This is a master class on optimization techniques from Intel for accelerating deep-learning workloads. The workshop takes attendees through the optimizations calibrated for PyTorch*, an installation guide, and the performance-boost number. Learn about the ease of use for the Python* API, vectorization, parallelism, quantization, operator fusion, constant folding, and more.
Intel will demonstrate:
- Intel® Optimization for PyTorch* and its release in the Intel® oneAPI AI Analytics Toolkit.
- Intel® Extension for PyTorch* and how it targets optimizations on the Intel® Advanced Vector Extensions 512 instruction set.
March 25, 2022
3:00 p.m. - 5:00 p.m. (IST)
Explore the power of the Intel® oneAPI AI Analytics Toolkit to streamline development and optimization of machine-learning workloads across a hybrid cloud landscape with few (or no) code changes required.
Learn how to design and develop software for Intel® SoC FPGAs using Intel® Quartus® Prime Software. This course uses a remote computer connected through Webex* for labs. No setup is needed.
March 23-24
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
Learn how to use the Intel® Quartus® Prime Pro Edition Software to develop an FPGA and correlate these steps to tools from other vendors.
March 23-24
9:00 a.m.-1:30 p.m. PDT (Pacific daylight time)
Learn how to accelerate deep learning applications—natural language processing, recommender systems, computer vision, and more—on Intel® CPUs and GPUs with the Intel® Extension for PyTorch*.
Learn the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. The course uses a remote computer connected through Webex* for labs. No setup is needed.
March 15-16
10:00 a.m.-2:30 p.m. CET (Central European time)
Attend this 40-minute lecture and three-hour instructor-led course to learn how FPGAs work. Explore the associated design flow using Intel® Quartus® Prime Software.
March 14
8:00 a.m.-12:00 p.m. PDT (Pacific daylight time)
Learn the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. The course uses a remote computer connected through Webex* for labs. No setup is needed.
March 9-10
9:30 a.m.-1:30 p.m. PST (Pacific standard time)
Learn to quickly build designs for Intel® FPGAs using the system-level integration tool, Platform Designer, which is part of Intel® Quartus® Prime Software. Increase your proficiency with the software and learn how to integrate off-the-shelf intellectual property and custom logic into a system.
March 9-10
9:00 a.m.-1:30 p.m. PST (Pacific standard time)
Learn how to use the Intel® Quartus® Prime Pro Edition Software to develop an FPGA from its initial design to programming the device. This course uses a remote computer connected through Webex* for labs. No setup is needed.
March 2-3
9:00 a.m.-1:30 p.m. PST (Pacific standard time)
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer feature in Intel® Quartus® Prime Pro Edition Software. This course uses a remote computer connected through Webex* for labs. No setup is needed.
March 2-3
9:00 a.m.-1:30 p.m. PST (Pacific standard time)
As FPGA designs become more complex, a larger part of development time is spent verifying designs. You will use a remote computer connected through Webex* for labs. No set up is needed. February 28-March 1, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software. You will use a remote computer connected through Webex* for labs. No setup is needed. February 28-March 1, 10:00 a.m. - 2:30 p.m. central European time (CET)
In this class, you will learn how to use the Intel® HLS Compiler to synthesize, optimize, and verify design components for Intel FPGAs. You will use a remote computer connected through Webex* for labs. No set up is needed. February 23-24, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn how to use the Intel® Quartus® Prime Pro Edition Software to develop an FPGA from its initial design to programming the device. You will use a remote computer connected through Webex* for labs. No set up is needed. February 21-22, 10:00 a.m.-2:30 p.m. Central European Time (CET)
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. You will use a remote computer connected through Webex for labs. No setup is needed. February 16-17, 9:00 a.m.-1:30 p.m. Pacific time (PT)
You will learn how to use the Intel® Quartus® Prime Pro Edition software to develop an FPGA design, and correlate these steps to tools from other vendors. You will use a remote computer connected through Webex* for labs. No set up is needed. February 16-17, 9:00 a.m.-1:30 p.m. Pacific time (PT)
This instructor-led course consists of a forty minute lecture and 3 hour instructor-led explaining how FPGAs work and the associated design flow using the Intel® Quartus® Prime Software. February 14, 8:00 a.m.-12:00 p.m. Pacific time (PT)
This class will teach you how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool, part of the Intel Quartus® Prime software. You will become proficient with using Platform Designer and learn how to quickly integrate “off-the-shelf” IP and custom logic into a system. February 9-10, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Find out the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed. February 9-10, 9:00 a.m.-1:30 p.m. Pacific time (PT)
If you’re a graphics application engineer, this is a do-not-miss session. Find out how a free, open-source development tool can help you improve the features and performance of your volume-rendering applications on Intel® processors.
9:00 a.m. PST
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. You will use a remote computer connected through Webex for labs. No setup is needed. February 7-8, 10:00 a.m.-2:30 p.m. Central European Time (CET)
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software. You will use a remote computer connected through Webex* for labs. No setup is needed. February 2-3, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Find out the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed. January 31-February 1, 10:00 a.m.-2:30 p.m. central European time (CET)
As FPGA designs become more complex, a larger part of development time is spent verifying designs. You will use a remote computer connected through Webex* for labs. No set up is needed. January 26-27, 9:00 a.m.-1:30 p.m. Pacific time (PT)
You will learn how to use the Intel® Quartus® Prime Pro Edition software to develop an FPGA design, and correlate these steps to tools from other vendors. You will use a remote computer connected through Webex* for labs. No set up is needed. January 26-27, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Find out how you can create a video processing IP core in 1/10 the time compared to using traditional RTL development and achieve 93% QoR.
9:00 a.m. PST
This class will teach you how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool, part of the Intel Quartus® Prime software. You will use a remote computer connected through Webex* for labs. No set up is needed. January 19-20, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Performance optimization is a bit like solving a mystery: it can get tricky unless you know where to look. This session shines a light on a key profiling tool that helps you do exactly that, whether you’re targeting one or multiple architectures.
9:00 a.m. PST
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software. You will use a remote computer connected through Webex* for labs. No setup is needed.January 17-18, 10:00 a.m. - 2:30 p.m. central European time (CET)
Find out the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed. January 12-13, 9:00 a.m.-1:30 p.m. Pacific time (PT)
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. You will use a remote computer connected through Webex for labs. No setup is needed. January 12-13, 9:00 a.m.-1:30 p.m. Pacific time (PT)
This instructor-led course consists of a forty minute lecture and 3 hour instructor-led explaining how FPGAs work and the associated design flow using the Intel® Quartus® Prime Software. January 10, 8:00 a.m.-12:00 p.m. Pacific time (PT)
Learn how to use the Intel® Quartus® Prime Pro Edition Software to develop an FPGA from its initial design to programming the device. You will use a remote computer connected through Webex* for labs. No set up is needed. January 10-11, 10:00 a.m.-2:30 p.m. Central European Time (CET)
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software. You will use a remote computer connected through Webex* for labs. No setup is needed. January 5-6, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn how to use the Intel® Quartus® Prime Pro Edition Software to develop an FPGA from its initial design to programming the device. You will use a remote computer connected through Webex* for labs. No set up is needed. January 5-6, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Are you interested in powerful hardware accelerators and developing high-performance applications? If so, then this virtual workshop is for you.
6:00 p.m. - 9:00 p.m. India Standard Time
Learn how to use the Nios® processor, Platform Designer system development tool, and Nios® II Embedded Design Suite (EDS) to create a customized embedded system. December 13, 8:00 a.m.-12:00 p.m. Pacific time (PT)
KubeCon + CloudNativeCon and Open Source Summit combine together for one event in China. KubeCon + CloudNativeCon gathers all CNCF projects under one roof. Join leading technologists from open source cloud native communities to further the advancement of cloud native computing.
Find out the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed. December 8-9, 9:00 a.m.-1:30 p.m. Pacific time (PT)
It’s coming. The 2022 release of Intel® oneAPI tools will be available mid-December 2021. Get an advance peek of what’s new, plus engage in a live Q&A with Intel engineers about all things oneAPI.
Whether you have one Intel oneAPI tool or all 36 of them, this webinar is for you.
December 8, 9:00 a.m. Pacific standard time (PST)
Find out the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed. December 6-7, 10:00 a.m.-2:30 p.m. central European time (CET)
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software. You will use a remote computer connected through Webex* for labs. No setup is needed. December 1-2, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software. You will use a remote computer connected through Webex* for labs. No setup is needed. November 29-30, 10:00 a.m. - 2:30 p.m. central European time (CET)
Connect with us in Las Vegas as one of the sponsors of this years event.
Sri Harsha Gajavalli talks about the Intel® Distribution of OpenVINO™ toolkit that helps accelerate AI workloads including computer vision, audio, speech, language, and recommendation systems. It also enables you to deploy high-performance applications and algorithms across various Intel® architecture including CPUs, integrated and discrete GPUs, VPUs, and FPGAs from edge to cloud. November 28, 11:00 a.m. - 12:00 p.m. India Standard Time (IST)
Join Intel® Innovators for an in-depth technical exploration of the Intel® Edge Software Hub at this developer meetup. November 24, 10:00 a.m. - 5:00 p.m. South African Standard Time (GMT+2)
This instructor-led course explains how FPGAs work and their associated design flow using the Intel® Quartus® Prime Software. November 22, 8:00 a.m.-12:00 p.m. Pacific time (PT)
Oluwatobi Oyinlola talks about the Intel® Distribution of OpenVINO™ toolkit that helps accelerate AI workloads including computer vision, audio, speech, language, and recommendation systems. It also enables you to deploy high-performance applications and algorithms across various Intel® architecture including CPUs, integrated and discrete GPUs, VPUs, and FPGAs from edge to cloud. November 20, 11:00 a.m. - 6:00 p.m. West Africa Standard Time (GMT +1)
Location: Tai Solarin University, Ijagun, Ijebu-Ode, Nigeria
Find out how to tune your software for optimal performance after the hardware is available using the performance-analysis workhorse, Intel® VTune™ Profiler.
Learn how to use the Intel® Quartus® Prime Pro Edition Software to develop an FPGA from its initial design to programming the device. You will use a remote computer connected through Webex* for labs. No set up is needed. November 17-18, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Find out the techniques used by FPGA design specialists to close timing on designs that extend the limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed. November 15-16 10:00 a.m. - 2:30 p.m. Central European Time (CET)
Join the hands-on tutorials, technical talks, and panels spanning the oneAPI programming model, AI analytics, performance analysis tools, and libraries with global industry experts from Berkeley, Argonne National Laboratory, NASA, Codeplay*, University of Lisbon, University of Edinburg and more. Get the latest information on Intel® oneAPI toolkits since their initial production release in late 2020.
Learn streamlined methods for implementing a 1D Fourier correlation to perform complex mathematical operations that require multiple kernel functions.
Get a general introduction to the Verilog HDL and its use in programmable logic design, covering the basic constructs used in simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed. November 10-11, 9:00 a.m.-1:30 p.m. Pacific time (PT)
Learn how to design devices with the Intel® SoC FPGA using Intel® Quartus® Prime Software and how to develop software for these devices. You will use a remote computer connected through Webex* for labs. No set up is needed. November 10-11 9:00 a.m. - 1:30 p.m. Pacific Time (PT)
Join Intel for a two-day online training to explore the workflow using the Intel® Distribution of OpenVINO™ toolkit, and learn about support for accelerating deep-learning algorithm deployment in your applications. Learn how to optimize and improve performance with various tools included in the toolkit. Experience different Intel hardware for the deep-learning workload on Intel® DevCloud for the Edge.
Learn how to constrain and analyze an FPGA design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro Edition Software. You will use a remote computer connected through Webex* for labs. No setup is needed. November 8-9, 10:00 a.m. - 2:30 p.m. central European time (CET)
Python’s stock scikit-learn is an efficient machine-learning library for predictive data analysis, but it is slow on today’s powerful hardware. Find out how the software optimizations inherent in the Intel® Extension for Scikit-learn* delivers 2x better performance with just two lines of code.
Join this exciting, new educational technology event series for developers and industry insiders, and immerse yourself in the latest trends and technologies to deliver AI, 5G, edge, cloud, and PC solutions with speed and real-world scale. Connect with Intel leaders and industry experts to gain the perspectives and training required to shift what’s possible through technology—today and tomorrow.
Learn how to design software for CPU-to-GPU offload—plus how to optimize the GPU code—using the intuitive user interface of Intel® Advisor. Part 1 of a 2-part series.
This online training gives an overview and practical application of the OpenVINO™ toolkit, and demonstrates features of the Intel® DevCloud.
Watch our demos and sessions from this year's Kubecon North America. Topics range from Securing Service Mesh to Better Observability with OpenTelemetry to Cloud First Client and more.
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