Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  DSP   |   External Memory   |   Embedded Processing   |   High-Speed Serial I/O   |   Parallel I/O   |   Signal Integrity   |   System Integration  

 Signal Integrity Features
      Plug & Play Signal Integrity
  
 Tools and Models
      Power Distribution Network
  
 Device Signal Integrity
      Stratix IV
      Stratix III
      Stratix II
   Stratix II GX
      Cyclone III
      Cyclone II
      Stratix GX
      Arria GX
  
 SI Education
      Signal Integrity Basics
      High-Speed Glossary
      Dr. Eric Bogatin
  
 Signal Integrity Partners
      Design Services
  

Arria GX FPGA Signal Integrity Center

ArriaTM GX FPGAs deliver solid signal integrity by providing transceivers with excellent jitter characteristics on a flip-chip package.

Arria GX Transceiver Features

The protocol-specific transceivers are tuned to meet and exceed standards compliancy with the following features:

  • Serial transceiver channels with clock/data recovery support operating speeds up to 3.125 Gbps
  • Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels
  • Support for CDR-based bus standards such as PCI Express, Gigabit Ethernet, and Serial RapidIO® 
  • 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
  • Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation
  • 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers
  • Refer to the transceiver block characteristics in the Arria GX device data sheet (PDF) for DC and switching specifications


Figure 1. Arria GX Transceiver at 2.5 Gbps

Figure 1. Arria GX Transceiver Performance at 2.5Gbps

Arria GX Signal Integrity Features

Table 1 provides a list of the signal integrity features in Arria GX devices to support the FPGA architecture and to simplify PCB design.

Table 1. Arria GX FPGA Architecture Signal Integrity Features

Feature

Specification Benefits
LVDS Dynamic Phase Alignment (DPA) Source-synchronous I/O operation up to 1.25 Gbps
  • Compensates for skew in board layout, allowing source-synchronous I/O to operate at higher data rates
  • Increases likelihood of successful PCB layout
Enhanced Simultaneous Switching Noise (SSN) Support Increased power/ground/pin ratio and enhanced package design
  • Reduces the risk of SSN because of high edge-rate signals when using high-speed bus interfaces
  • Arria GX FPGAs provide even greater signal, I/O pin, and ground ratio to counter additional transceiver requirements
On-Chip Termination Selectable on-chip termination resistors (100, 120, or 150 Ω)
  • Reduces reflections and maintains signal integrity on a variety of transmission media
  • Simplifies board design by
    minimizing the number of external termination resistors required

Documentation


View the Arria™ GX QuickCast Now

Download the Arria™ GX Handbook

  Please Give Us Feedback