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Home > Technology Center > Parallel I/O Print This Page Subscribe to Email Parallel I/O Altera provides a comprehensive I/O interface solution with support for a variety of single-ended and differential I/O standards, external memory, and high-speed interfaces to meet your high-bandwidth system requirements. Devices Stratix® IV GX FPGAs Stratix IV I/O Connectivity Single-Ended I/O Standards Dynamic On-Chip Termination External Memory Device Interfaces  Stratix III FPGAs Stratix III I/O Connectivity Single-Ended I/O Standards Dynamic On-Chip Termination Stratix II GX FPGAs Source-Synchronous Signaling Source-Synchronous Protocols Single-Ended I/O Standards External Memory Device Interfaces On-Chip Termination Stratix II FPGAs Source-Synchronous Signaling Source-Synchronous Protocols Single-Ended I/O Standards External Memory Device Interfaces On-Chip Termination Stratix GX FPGAs  Source-Synchronous Signaling Source-Synchronous Protocols System Applications Single-Ended I/O Standards External Memory Device Interfaces On-Chip Termination Stratix FPGAs  Differential and Single-Ended I/O Standards High-Speed Interfaces External Memory Device Interfaces On-Chip Termination Cyclone® III FPGAs Cyclone III I/O Connectivity On-Chip Termination External Memory Device Interfaces Cyclone II FPGAs  Cyclone II I/O Support Cyclone II Interfaces and Protocol Support External Memory Device Interfaces On-Chip Termination Cyclone FPGAs  Differential and Single-Ended I/O Standards External Memory Device Interfaces ArriaTM GX FPGAs High-Speed, Source-Synchronous Differential I/O Interface (PDF)  Selectable I/O Standards in Arria GX Devices (PDF)  External Memory Interfaces in Arria GX Devices (PDF)    Software Quartus® II Software   Protocols and  Intellectual Property SPI-4.2 RapidIO® Standard HyperTransport™ Standard Communications Intellectual Property (IP) Cores Interfaces and Peripherals IP Cores Digital Signal Processing (DSP) IP Cores Embedded Processors IP Cores Communication Standards Consortium Interfaces and Peripherals Standards Consortium DSP Standards Consortium   Design Examples Bus and I/O Design Examples   Literature IP Communications Literature Interfaces and Peripherals Literature   Training Altera® Technical Training Courses Fundamental Design Techniques for Stratix Devices Advanced Design Techniques for Stratix Devices Designing with Cyclone and Cyclone II Devices   Support Board Design Guidelines Solution Center Online Technical Support Rate This Page

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