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Home > Technology Center > External Memory > Cyclone III Print This Page Subscribe to Email Cyclone III FPGA External Memory Resources Cyclone® III FPGAs support a broad range of external memory interfaces, such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM.  Each of the memory standards below is supported by a new self-calibrating datapath available as a megafunction (altmemphy) that removes process variation and compensates for voltage and temperature variations to achieve data rates up to 400 Mbps and ease timing closure. Table 1. Cyclone III FPGA Maximum Clock Rate Support for External Memory Interfaces Memory Type Maximum Data Rate (per pin) Maximum Clock Frequency DDR2 SDRAM 400 Mbps 200 MHz DDR SDRAM 333 Mbps 167 MHz QDRII SRAM 333 Mbps 167 MHz Table 2 lists reference resources for additional information on Cyclone III FPGA external memory. Table 2. Cyclone III FPGA External Memory Resources Collateral Description Start Here Interfacing DDR & DDR2 SDRAM with Cyclone III FPGAs (PDF) Describes the interface architecture, signals, and timing analysis for a DDR/DDR2 SDRAM memory Device Selection Selecting the Right High-Speed Memory Technology for Your System (PDF) Describes how to select the right memory for your application External Memory Interfaces (PDF) Describes Cyclone III FPGA internals such as DDR Memory Interface Pins, DQS Phase-Shift circuitry and DDR Registers. Intellectual Property (IP)/Megafunction User Guides altmemphy Megafunction User Guide (PDF) Describes the altmemphy megafunction functionality and how to interface with Altera's DDR and DDR2 SDRAM high-performance controllers and third-party controllers. DDR/DDR2 SDRAM Controller Compiler User Guide (PDF) Describes the controller interface and also the design flow using SOPC builder and MegaWizard® Plug-In manager IP MegaStoreTM The web page links to different IP cores provided by Altera and partners. The web page also allows you to search for an IP of your interest. Timing Analysis TimeQuest Timing Analyzer (PDF) Learn about the features of the TimeQuest timing analyzer and how to constrain your design with SDC commands Constraining and Analyzing Timing for External Memory Interfaces in Stratix® III and Cyclone III FPGAs (PDF) Learn how to quickly meeting timing with your external memory interfaces. TimeQuest Resources This page provides links to resources for you to learn more about the TimeQuest timing analyzer. Models and Board Design Guidelines Board Design Guidelines Solution Center (Cyclone III FPGA Information Available Soon) The web page provides you with board design-related resources for Altera® devices. Its goal is to help you implement successful high-speed PCBs that integrate Altera device(s) and other elements. HSPICE Models (Cyclone III FPGA Information Available Soon) Web page listing of all the HSPICE models for Altera devices IBIS Models (Cyclone III FPGA Information Available Soon) Web page listing of all the IBIS models for Altera devices Kits and Boards Cyclone III FPGA Starter Kit The economical Cyclone III FPGA Starter Kit is an easy to use, yet comprehensive development kit. Rate This Page

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