SPI-4.2
The system packet interface level 4, phase 2 (SPI-4.2) protocol (alternatively known as POS-PHY Level 4 or PL4) continues to gain broad industry acceptance as the standard interface for packet and cell transfers between PHY and link layer devices in multi-gigabit applications. This includes asynchronous transfer mode (ATM) and packet over SONET/SDH (STS-192/STM-64), 10-Gigabit Ethernet, and multi-channel Gigabit Ethernet. Figure 1 shows the SPI-4.2 topology.
Figure 1. SPI-4.2 Topology
Notes:
- CDR = clock data recovery
- SERDES = serializer/deserializer
- POS = packet over SONET
The Altera® solution provides the greatest flexibility available. Single- or multi-port configurations are supported, with a variety of FIFO sizes and structures that allow shared or independent buffers. A number of data bus widths are also supported. Multiple burst sizes, the availability of an “almost-empty” FIFO flag, and support for continuous burst mode illustrate the breadth of support allowing greater optimization for a given application. The AtlanticTM interface allows easy interconnect to other intellectual property (IP) modules without intervening glue logic, and the IP Toolbench and MegaWizard® Plug-Ins make the customization of the core during system design easy, and minimize design time.
By supporting SPI-4.2 performance as high as 1 Gbps, ensures not only that mainstream data rate applications can be accomplished with comfortable margins or in less expensive lower-speed-grade devices, but that leading-edge, future-oriented designs can also be realized with currently available technology. At these speeds, the challenge of managing skew becomes significant. Stratix® GX FPGAs were the first FPGAs with embedded deskewing circuitry known as dynamic phase alignment (DPA) supporting data transfer rates as high as 1 Gbps. By embedding this function, you can realize the benefits of DPA without having to dedicate FPGA logic to it.
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