Altera's Serial RapidIO Solutions
Integrated Serial RapidIO Solutions
Altera provides a range of complete FPGA solutions for the development of custom RapidIO® processing elements, bridges, and switches. Device and intellectual property (IP) support is available for x1, x4, and 8-bit parallel. The solutions, which include configurable RapidIO IP cores and development boards, allow you to concentrate on the core functions of the system design by providing:
- Simple and fast protocol implementation
- Reduced design risks
- Shortened development times
Stratix® IV GX FPGAs, HardCopy® IV GX ASICs, Stratix II GX FPGAs, and Arria® GX FPGAs feature a fully integrated RapidIO solution. Embedded transceivers support the physical layers of the protocol, while the transport and logical layers are supported in IP, allowing the protocol to be implemented in a single device. Table 1 gives an overview of the complete RapidIO solution for Stratix IV GX FPGAs, HardCopy IV GX ASICs, Stratix II GX FPGAs, and Arria GX FPGAs.
External Transceiver-Based Serial RapidIO Solutions
For high-volume, cost-sensitive applications, use Cyclone® III and Cyclone II FPGAs with an external transceiver (or PHY device). Use high-density Stratix IV E FPGAs, HardCopy IV E ASICs, Stratix III FPGAs, HardCopy III ASICs, Stratix II FPGAs, and HardCopy II ASICs in applications requiring the highest density and performance. Table 2 shows Altera FPGAs with external PHY solutions for the RapidIO standard.
Technology Background
RapidIO is a high-performance, point-to-point, packet-switched interconnect technology defined by the RapidIO Trade Association. RapidIO transmits data and control information between microprocessors, digital signal processing (DSP) functions, communication or network processors, and I/O devices in embedded systems. Figure 1 illustrates a typical subsystem in a wireless application.
Figure 1. Serial RapidIO Topology in a Wireless Subsystem
Full-duplex point-to-point links are established with single or multiple high-speed serial lanes (1x and 4x are currently defined), and industry-standard 8B/10B-encoded data transmission at signaling rates of 1.25, 2.50, or 3.125 Gbaud for peak bandwidth of up to 20 Gbps. The initial RapidIO specifications were based on source-synchronous clocking (or bit-parallel clock and data), but subsequent specifications have adopted serialized clock and data transmission to reduce pin requirements and extend signal reach, making the Serial RapidIO standard well-suited for chip-to-chip, board-to-board, and backplane interconnects.
Related Links
Devices
Partners and Press Releases
- Tsi568A Serial RapidIO Switch Now Sampling, Tundra, May 17, 2005—Provides proven interoperability with systems, boards, and products, including the Altera Serial RapidIO MegaCore function in a Stratix GX FPGA and the Freescale PowerQUICC III (MPC8548)
Protocol Standard
|
Literature
> 
