Gigabit Ethernet
Altera provides a range of complete solutions to accelerate design cycles for FPGAs that use Gigabit Ethernet ports for chip-to-chip, board-to-board, or backplane interconnect. Altera offers solutions for use within embedded systems or for networking over copper or fiber optic media. The solutions enable simple and fast protocol implementation to reduce design risk, shorten development times, and allow you to concentrate on the core functions of the system design.
Gigabit Ethernet Integrated Solutions
Stratix® IV GX FPGAs, HardCopy® IV GX ASICs, Stratix II GX FPGAs, and Arria® GX FPGAs provide a fully integrated Gigabit Ethernet solution. The embedded transceivers fully support IEEE 802.3 Gigabit Ethernet physical coding sublayer (PCS) and physical medium attachment (PMA) layers of the protocol that, when combined with Altera’s Triple-Speed Ethernet MegaCore® function, allow the protocol to be implemented in a single device. Table 1 gives an overview of the complete Gigabit Ethernet solution.
External Transceiver Solutions
Use Cyclone® III and Cyclone II FPGAs with an external transceiver (or PHY device) for high-volume, cost-sensitive applications, and use high-density Stratix IV E FPGAs, HardCopy IV E ASICs, Stratix III FPGAs, HardCopy III ASICs, Stratix II FPGAs, and HardCopy II ASICs in applications requiring the highest density and performance. Table 2 shows the Altera FPGA solutions when using an external PHY. Connectivity is provided via an industry standard GMII or RGMII interface. You can configure Altera’s Triple-Speed Ethernet MegaCore function onto Cyclone III and Stratix III FPGAs for external PHY operation, providing an integrated solution.
| Table 2. External PHY Solutions for Gigabit Ethernet |
| Solution |
Description |
| Devices |
Stratix IV E FPGAs, HardCopy IV E ASICs, Stratix III FPGAs, HardCopy III ASICs, Stratix II FPGAs, HardCopy II ASICs, Cyclone III FPGAs, Cyclone II FPGAs |
| Physical Interface |
Cyclone II, Stratix II, and HardCopy II devices support Gigabit Ethernet MAC ports with a GMII or RGMII interface and an external transceiver |
| Gigabit Ethernet IP Core |
Gigabit Ethernet IP Cores |
| Development Board |
Nios® II Development Kit, Cyclone II Edition and Nios II Development Kit, Stratix II Edition with MoreThanIP 10/100/1000 Ethernet PHY Daughterboard with Marvell PHY
|
Technology Background
Ethernet was originally defined as a LAN technology to interconnect client PCs at line rates of 10 Mbps through switches (also known as hubs). Over the years, client line rates increased to 100 Mbps (Fast Ethernet) and switches supporting 1,000 Mbps (Gigabit Ethernet) line rates emerged to interconnect multiple 10/100 Ethernet hubs. The near ubiquitous use of Ethernet technologies in LANs has resulted in significant economies of scale, driving down the component costs, including the switch devices.
Today, Gigabit Ethernet is a cost-effective technology when used to do the following:
- Connect multiple devices to a local CPU
- Interconnect multiple boards across a backplane for data
- Control signaling between line cards and the host CPU within an embedded system
Figure 1 shows a typical 10-Gbps line card using a Stratix II GX FPGA for backplane interconnect, including the Stratix II GX Gigabit Ethernet MAC for control signaling to the host CPU.
Figure 1. Stratix II GX Gigabit Ethernet MAC in a Control Plane Application
Related Links
Devices
Gigabit Ethernet Protocol Standard
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Literature
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