1080p Video Design Framework
With their inherently parallel digital signal processing (DSP) blocks, an abundance of embedded memory blocks, a large number of registers, and high-speed memory interfaces, FPGAs are ideal for high definition (HD) video system design.
Altera developed a video design framework that enables the fastest design cycle for video application. The components of this framework are:
- A library of basic building block video image processing intellectual property (IP) cores designed for easy plug-and-play type interface
- A low-overhead streaming video interface protocol, which is available as an open standard
- System tools such as SOPC Builder that allow for an automated way of generating control and arbitration logic
- A suite of HD reference designs that can be used as a starting point for your video datapath designs
Figure 1 shows the suite of IP cores that are part of a video image processing suite of IP cores. This suite provides IP that ranges in complexity from a color space converter to a polyphase scaler and motion adaptive de-interlacer.
Figure 1. Complete Suite of Video Image Processing IP
The Avalon® Streaming interface (ST) video protocol is designed for sending data and control data from one video processing block to the other.
This protocol is open and the specification is freely downloadable via the web. Using this specification does not in any way lock you to Altera® FPGAs, but all the Altera video IP and video reference designs utilize this interface.
Figure 2 shows how different video functions can be connected using this protocol. More information on this protocol is available in the ‘Interface’ section of the Video and Image Processing Suite User Guide (PDF).
Figure 2. Avalon ST Protocol for Video Interfaces and Avalon Memory Mapped (MM) Protocol for Control Plane Interfaces
Video systems almost always include an embedded processor and a memory subsystem to manage the video frames in the external memory. The SOPC Builder system tool provided by Altera greatly simplifies embedded system design. This tool includes a library of elements such as soft core processors (Nios® II), interfaces, memory, bridge, and DSP IP cores. It also features a connectivity GUI and generator to automatically wire up arbitrated and streaming bus systems.
Figure 3. SOPC-Based Design Flow for Video Datapaths
Finally, the entire video design framework really comes together in the form of an HD reference design that showcases the actual video processing common to many applications. Altera developed several reference designs that were driven by actual customer demand for scaling, mixing, and processing HD video streams over serial digital interfaces (SDI).
Figure 4 shows one of the reference designs, which was displayed at the NAB Show 2008 in Las Vegas. This design, which processes 1080p quality video, was built using the Altera video design framework. For more details on this design contact your local Altera FAE.
Figure 4. HD Quality Reference Designs to Speed Development
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