Implement High Performance DSP Designs FASTER than ever before
The latest version of DSP Builder features the advanced blockset capability which allows timing-driven Simulink synthesis. This technology lets you achieve high-performance design implementations, running at near-peak FPGA performance in a matter of minutes—compare that to the hours, if not days, required to hand-optimize HDL code.
With the DSP Builder advanced blockset, building high-performance complex digital signal processing (DSP) signal chains becomes as simple as 1-2-3 (see Figure 1):
- Set the required system level constraints—in this case, the clock rate for a 6-channel, 128-tap finite impulse response (FIR) filter is specified at 403 MHz within Simulink
- Choose the target FPGA family—since different device families might have different DSP block architecture, this information has to be incorporated by the synthesis tool
- Click RUN
Figure 1. Build a High-Performance Filter in Three Easy Steps
DSP Builder advanced blockset synthesizes the Simulink description of the signal chain—taking into account the system-level timing constraints specified (in this case, 403.2 MHz). Using the built-in timing models for each FPGA and the performance of the intellectual property (IP) blocks, the tool adds pipeline registers and control logic as necessary to achieve the clock rate provided.
The result (shown in Figure 2) is a 6-channel FIR filter with realized system performance of 408 MHz—all this without touching the HDL code.
Figure 2. Automatically Generated Timing Optimized HDL
This capability is critical for designing multi-channel signal processing datapaths in applications such as multi-carrier, multi-antenna RF processing in wireless applications.
It automatically adds pipelined stages and registers, and implements time division multiplexing to generate highly optimized designs for functions such as digital upconversion (DUC), downcoversion (DDC), crest factor reduction (CFR) and digital predistortion (DPD). DSP Builder version 8.0 includes design examples for multi-antenna, multi-carrier WiMAX and WCDMA DUC and DDC designs.
Get DSP Builder advanced blockset training today!
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