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Home > Support > Design Software > Board Level Tools > HSPICE Simulation Print This Page Subscribe to Email Generating HSPICE Simulation Deck Files for External Signal Integrity Analysis To generate HSPICE Simulation Deck files (.sp) in the Quartus II software to perform board-level signal integrity verification in other EDA tools: On the Assignments menu, click Settings. In the Category list, select Board-Level under EDA Tool Settings. In the Board-Level Signal Integrity Analysis box, select HSPICE from the Format list. Type or browse to the location you want to use as the output directory for the HSPICE Simulation Deck files. The default location is <project directory>/board/hspice. To generate the HSPICE Simulation Deck files, compile the design. Notes:   The Quartus II software can generate HSPICE Simulation Deck files for supported device families. For all other families, refer to the HSPICE models section of the Signal Integrity section on the Altera website.   The EDA Netlist Writer places the HSPICE Simulation Deck files in the specified directory. If you have already compiled the design, and want to specify different EDA tools settings and generate output files without recompiling the design, on the Processing menu, point to Start and then click Start EDA Netlist Writer. Use the HSPICE Simulation Deck files to perform board-level signal integrity verification with the Synopsys HSPICE circuit simulator software.     Rate This Page

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