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Home > Support > Design Software > HardCopy Design Print This Page Subscribe to Email Quartus II Design Software Support Resources for HardCopy Series ASICs Using Quartus® II design software, you can leverage a Stratix® series FPGA as a prototype and seamlessly migrate your design to HardCopy® series ASICs for volume production. Table 1 lists Quartus II software support resources for HardCopy series ASICs. The HardCopy Series Handbook provides detailed information about HardCopy series ASICs and the design flows supported in Quartus II software.  Table 1. Quartus II Support for HardCopy Series ASICs Resource Description Quartus II Support for HardCopy II Devices (PDF) Chapter in the HardCopy Series Handbook. Quartus II Support for HardCopy Stratix Devices (PDF) Chapter in the HardCopy Series Handbook. FindAnswers on HardCopy Devices FindAnswers is a natural language processing technology that provides answers to common technical problems, including HardCopy device-related issues. ASIC to FPGA Design Methodology & Guidelines (PDF) Provides important guidelines to migrate designs from ASIC to FPGA. HardCopy Device Questions and Answers Lists commonly asked HardCopy device questions and answers. Training Courses and Demonstrations HardCopy Prototype Design (Demo) View a short demonstration on designing with HardCopy series devices in Quartus II software. HardCopy File Preparation (Demo) View a short demonstration on designing with HardCopy series devices in Quartus II software. HardCopy II Architecture and Design Flow (Online Course) This class allows you to make design decisions based on the discussed HardCopy II device architecture. You will learn the Stratix II to HardCopy II design flow and use the HardCopy II design advisor in the Quartus II software v. 7.1 as a guide to carry you through the migration process. This is a 1.5 hour online course. HardCopy II Devices: Design Guidelines (Online Course) This class teaches you how to follow design guidelines to get the best possible implementation for your HardCopy II device. Some of the important details of design assistant are discussed, and solutions to common problems are outlined. You will learn about timing closure and fitting techniques and the corresponding Quartus II version 7.1 settings. Finally, you will learn how to constrain source synchronous SDR interfaces. This is a 1 hour online course. Designing with HardCopy II Devices (Instructor-led Course) Learn how to implement a HardCopy II ASIC using a Stratix II FPGA as a prototyping vehicle. Rate This Page

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