Design Entry and Planning Resource Center
Altera provides guidelines on planning and structuring your design, as well as HDL coding styles that can have a significant effect on your design's quality of results. For additional information on design entry and design planning, as well as design and coding guidelines, see:
For a brief overview of Quartus® II design entry features, refer to the Design Features product page.
To search for known design-related issues and technical support solutions, use Altera’s Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
Design Entry and Planning Resources
Table 1 provides links to available documentation on design entry and planning.
| Table 1. Design Entry and Planning Documentation |
| Title |
Description |
| Design Planning with the Quartus II Software (PDF) |
This chapter of the Quartus II Development Software Handbook discusses important FPGA design planning issues, provides recommendations, and describes various tools available for Altera FPGAs to help you improve design productivity. |
| Design Recommendations for Altera Devices and the Quartus II Design Assistant (PDF) |
This chapter of the Quartus II Development Software Handbook describes synchronous design practices and recommended design techniques. It also describes the Quartus II design assistant that helps find potential design problems. |
| Recommended HDL Coding Styles (PDF) |
This chapter of the Quartus II Development Software Handbook provides Verilog HDL and VHDL coding style recommendations and examples, including inference of Altera megafunctions and device-specific coding guidelines. |
| Designing with Low-Level Primitives User Guide (PDF) |
This user guide describes low-level HDL design techniques using small architectural building blocks and assignments to specify a particular hardware implementation. |
Advanced Synthesis Cookbook: A Design Guide for Stratix II and Stratix III Devices (PDF)
Design Files (ZIP) |
This user guide discusses hand-crafted techniques you can use to optimize design blocks for the adaptive logic modules (ALMs) in Stratix® II and Stratix III devices. The document includes a collection of circuit building blocks and related discussions, and each section includes a list of example design files that you can use for testing and to better understand the derivation of the more complex optimizations. |
| Quartus II Integrated Synthesis (PDF) |
This chapter of the Quartus II Development Software Handbook documents the design flow and language support in the Quartus II software. It explains how to improve and control your synthesis results with Quartus II synthesis options, attributes, and other features. It also discusses node-naming conventions and how to preserve nodes through synthesis. |
Table 2 provides links to available training and demonstrations on design entry and planning.
| Table 2. Design Entry and Planning Training and Demonstrations |
| Title |
Description |
Design Entry
(Online Demonstration) |
You will see how to set up a project and enter a design in the Quartus II software.
This is a 3.5-minute demonstration. |
Design Planning Guidelines for High-Density FPGAs
(Online Course) |
You will learn how to avoid pin layout, power consumption, and timing issues with proper design planning techniques.
This is a 1-hour online course. |
| Best Practices for Incremental Compilation Partitions and Floorplan Assignments—Part 1 and Part 2(Online Courses) |
This training explains why and when to use incremental compilation. You will learn how to choose design partitions and follow guidelines to help you set up your design hierarchy and source code for incremental compilation.
Parts 1 and 2 are each 1-hour online courses.
|
VHDL Basics
(Online Course) |
You will get an overview of the VHDL language and its use in programmable logic design.
This is a 1-hour online course. |
Introduction to VHDL
(Instructor-Led Course) |
You will get a general introduction to the VHDL language and its use in programmable logic design. The emphasis is on the synthesis constructs of VHDL; however, you will also learn about the simulation constructs. You will gain a basic understanding of VHDL to enable you to begin creating your design. You will gain hands-on experience by implementing various simple but practical designs.
This is a 1-day instructor-led course. |
Advanced VHDL Design Techniques
(Instructor-Led Course) |
You will learn efficient coding techniques for VHDL synthesis, particularly for Altera devices. You will gain experience writing behavioral and structural code and learn how to effectively code common logic functions including registered, memory, and arithmetic functions.
This is a 1-day instructor-led course.
|
Verilog HDL Basics
(Online Course) |
You will get an overview of the Verilog HDL language and its use in programmable logic design.
This is a 1-hour online course.
|
Introduction to Verilog HDL
(Instructor-Led Course) |
You will learn how to implement basic constructs and modeling structures in Verilog to create an optimal FPGA design. The emphasis is on the synthesis constructs of Verilog HDL; however, you will also learn about the simulation constructs. You will also learn how to take advantage of various features in Verilog HDL such as delays in programmable logic design. You will gain hands-on experience by implementing various simple but practical designs.
This is a 1-day instructor-led course.
|
Advanced Verilog HDL Design Techniques
(Instructor-Led Course) |
You will learn efficient coding techniques for writing synthesizable Verilog, particularly for Altera devices. You will gain experience in writing behavioral and structural code and implementing state machines with multiple efficient coding styles. You will also learn how to optimize a design to an FPGA.
This is a 1-day instructor-led course.
|
|
Using the Quartus II Software: Schematic Design
(Online Course)
Chinese Version: Using the Quartus II Software: Schematic Design
(Online Course)
|
You will learn how to use the Quartus II software graphic editor to create a schematic design. You will learn how to utilize the library of functions installed with the Quartus II software (e.g., multipliers, filters, etc.). You will also learn how to generate your own custom functions.
This is a 30-minute online course.
|
|
Literature
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