Digital Predistortion Reference Design
from Altera Corporation
Please contact your local Altera sales representative for a copy of this reference design. The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Overview
Power amplifiers (PAs) for 3G wireless communication systems need high linearity at the PA output to achieve high adjacent channel leakage ratio (ACLR) and low error vector magnitude (EVM). High efficiency is desirable; however, when operating with high efficiency, PAs are at their most non-linear. Digital predistortion (DPD) is an efficient, cost-effective means of compensating for PA nonlinearity and retaining high efficiency.
The DPD reference design implements an adaptive lookup table (LUT)-based algorithm—commonly used for linearization of PAs. The design constantly applies correction values from a LUT to the incoming stream of samples. It also compares the measured output with the input, and uses this measurement to update the LUT, making the system adaptive.
For 3G systems, the DPD reference design operates up to four universal mobile telecommunications system (UMTS) channels and corrects the third and fifth order intermodulation products.
The reference design comprises of a MATLAB system simulation environment, including a graphical user interface (GUI). This environment allows you to custom configure the reference design algorithm, experiment with other algorithms, and apply stimuli. The MATLAB model of the design is a bit-accurate representation of the Verilog HDL solution.
Altera supplies the reference design as Verilog HDL source code. The reference design includes a Nios® processor subsystem, and testbenches that allow you to test the Verilog HDL with data generated by the MATLAB system simulation environment
Features
- MATLAB GUI allows configuration of the design &test conditions, &displays graphs of the results
- Bit-accurate MATLAB model of a DPD design
- Nios processor subsystem uses hardware acceleration
- Verilog HDL testbench compares the MATLAB-generated results with the results from the RTL simulation
- Verilog HDL source code for Nios processor, coordinate rotation digital computer (CORDIC) reference design, and DPD logic
Demonstrated Altera Technology
Block Diagram
Figure 1. Block Diagram of DPD using a Stratix II FPGA as an Example
Notes:
- FIR = finite impulse response
- DUC = digital upconverter
- DDC = digital downconverter
Related Links
Reference Designs Disclaimer
These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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