Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Knowledge Database   |   Devices   |   Design Software   |   Intellectual Property   |   Reference Designs   |   Design Examples   |   mySupport  

 Altera Troubleshooters
      Overview
      Licensing
      Simulating with ModelSim
      Timing Analysis
      PLL Loss of Lock
      FPGA Configuration
      JTAG Config & ISP
      PFL Troubleshooter
      Jam, JBC and SVF
      Usage Guidelines
      Optimization Advisor
  

Solution ID: rd01302008_207
Last Modified: Jul 29, 2008
Product Category: Devices
Product Area: Configuration
Product Sub-area: Configuration I/O

Problem

What is the setup time specification for the TDO pin of the USB-Blaster?

Solution

Altera® does not provide a setup time specification for the TDO pin of the USB-Blaster™, the setup time margin is guaranteed by design. The clock cycle is large in comparison to the setup time of Altera devices.

The TCK cycle frequency is approximately 6MHz or 167ns/cycle.

 Note that JTAG changes data on the negative edge of TCK and latches it on the positive edge of TCK

For example, in Stratix® devices, the TCK to TDO maximum delay is 14ns.


Feedback

 Rate This Page
     This solution answers my question:
Strongly Disagree
   
Strongly Agree
 
  1 2 3 4 5  
     This solution was easy to find:
Strongly Disagree
   
Strongly Agree
 
  1 2 3 4 5  

    Please provide additional feedback to improve support solutions:


Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.

  Please Give Us Feedback