|
Solution ID: rd01092008_374
Last Modified: Aug 01, 2008
Product Category: Devices
Product Area: I/O
Product Sub-area: Architecture/Features
Problem
Is there any performance reduction when using Cyclone III differential pin pairs that are not adjacent?
Solution
No, there is no performance reduction when using adjacent (adj) vs separate (sep) differential pin pairs in Cyclone® III devices. Separate pins are adjacent on silicon pads but not necessarily adjacent on the package balls, and they are generally split across different rows or columns as seen using the Pin Planner - Pad View in the Quartus® II software.
The positive (p) and negative (n) channels are matched to be within the published Fmax specifications.
Feedback
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
|
Literature
> 
