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Home > Support > Knowledge Database > Browse Knowledge Database Print This Page Subscribe to Email Browse Knowledge Database Product Category Product Area Product Sub-Area   Browsing all solutions. Results 1 - 10 of about 3645. Hide Description   Show 15  Show 100           Next 1 Can the user design logic access the JTAG USERCODE register that is loaded into the FPGA? No, there is no way to access the USERCODE via the design. You can only retreive the USERCODE via JTAG using the USERCODE command or with a JAM file. For more information on how t… altera.com/support/kdb/solutions/rd07162008_707.html - 2008-08-05 2 Can you use the Nios II Flash Programmer with HardCopy II devices? The Nios® II Flash Programmer can be used with HardCopy® II devices to program parallel CFI compliant flash devices.   For EPCS serial devices, the Nios II Flash Programmer … altera.com/support/kdb/solutions/rd06042007_901.html - 2008-08-05 3 Why are some pins in the M256 package of MAX II devices located in bank 1 (side bank) designated as EDGE_TOP instead of EDGE_LEFT in Quartus II software? Some pins in the M256 package of MAX® II devices located in bank 1 (side bank) are designated as EDGE_TOP instead of EDGE_LEFT in Quartus® II software because these pads are “… altera.com/support/kdb/solutions/rd07082008_925.html - 2008-08-05 4 Why do I receive an error message “Can’t access JTAG chain” when I configure a Cyclone III device in an EQFP E144 package? You may receive an error message “Can’t access JTAG chain” when you configure Cyclone® III devices in an EQFP E144 package. This is because all E144 packages have an expo… altera.com/support/kdb/solutions/rd07102008_776.html - 2008-08-05 5 Is there any performance reduction when using Cyclone III differential pin pairs that are not adjacent? No, there is no performance reduction when using adjacent (adj) vs separate (sep) differential pin pairs in Cyclone® III devices. Separate pins are adjacent on … altera.com/support/kdb/solutions/rd01092008_374.html - 2008-08-01 6 Are there any errors in the MAX+PLUS® II software version 9.3x Help regarding MAX® 7000AE devices? (MAX 7000AE) Both the Report File (.rpt) and the MAX 7000 Programmable Logic Device Family Data Sheet list correct pinout information. Yes. The I/O pinout information for 256-pin FineLine BGA… altera.com/support/kdb/solutions/rd10121999_9959.html - 2008-07-30 7 Do Altera simulation models support the programmable internal weak pull up resistor? No, Altera® device functional and timing simulation models do not have the programmable internal weak pull up option. To simulate the internal weak pull up option,… altera.com/support/kdb/solutions/rd06172008_116.html - 2008-07-29 8 Error: File /pfl_ep3c40.sof is corrupt The Quartus® II software version 8.0 may generate this error. This problem is fixed beginning with the Quartus II software version 8.0 SP1.  To avoid this error, do… altera.com/support/kdb/solutions/rd07282008_757.html - 2008-07-29 9 Is the USB software guard supported in the Windows 2000 operating system? The USB software guard is supported in the Windows 2000, Windows XP, and Windows Vista operating systems. The USB software guard is not supported in Windows NT 4.0.   Be… altera.com/support/kdb/solutions/rd03042005_966.html - 2008-07-29 10 What is the setup time specification for the TDO pin of the USB-Blaster? Altera® does not provide a setup time specification for the TDO pin of the USB-Blaster™, the setup time margin is guaranteed by design. The clock cycle is lar… altera.com/support/kdb/solutions/rd01302008_207.html - 2008-07-29   Next Rate This Page

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