Verilog HDL: Sum of Multiplication Fixed Coefficient Soft Multiplier
This design implements 4-bit input, 16-bit fixed coefficient sum of multiplication using M512 RAM blocks as look-up tables (LUTs). For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices (PDF).
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Table 1 shows the Sum of Multiplication Fixed Soft Multiplier design example port listing.
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Table 1. Sum of Multiplication Fixed Soft Multiplier Port Listing
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Port Name
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Type
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Description
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data_in[3..0]
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Input
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The input is a 4-bit value comprised of the four unique sum of multiplication inputs.
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sload_data
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Input
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Active high. Specifies the start of a new data set and new multiplication operation.
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clk
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Input
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Clock
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sclr
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Input
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Active high synchronous clear
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result[21..0]
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Output
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The output is a 22-bit signed value.
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result_valid
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Output
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Indicates when the output is the valid result of a complete multiplication. The signal will go high for the time that the output is valid.
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