Verilog HDL: Dual Clock Synchronous RAM
This example describes a dual clock synchronous 128-bit x 8-bit RAM design with different read and write addresses in Verilog HDL. Synthesis tools detect RAM designs in HDL code and infer altsyncram or altdpram megafunctions depending on the target device architecture.
Figure 1. Dual Clock Synchronous RAM Top-Level Diagram
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Table 1 lists the ports and gives a description for each.
| Table 1. Dual Clock Synchronous RAM Port Listing |
| Port Name |
Type |
Description |
d[7:0] |
Input |
8-bit data input to RAM |
clk1 |
Input |
Write clock |
clk2 |
Input |
Read clock |
addr_in[6:0] |
Input |
7-bit write address input to RAM |
addr_out[6:0] |
Input |
7-bit read address input to RAM |
we |
Input |
Write enable |
q[7:0] |
Output |
8-bit data output of RAM |
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