TimeQuest Example: Basic Source Synchronous Output
These examples show two ways you can constrain source synchronous output timing with Synopsys Design Contraint (SDC). To constrain source synchronous output timing, you must have a way to specify the output delay relative to the clock driving out of the FPGA.
Generated Clock
You can create a generated clock on the clock output port of your FPGA. A generated clock automatically computes the latency from its source clock. You must make the following three constraints to constrain the output for the simple circuit in Figure 1.
- A base clock driving the
clk_in port
- A generated clock on the
clk_out port
- An output delay constraint on the
data_out port, relative to the generated clock on the clk_out port.
Figure 1. Source Synchronous Constraints with a Generated Clock
The following SDC commands constrain the output.
# Define the input clock
create_clock -period 10 -name clk_100 [get_ports clk_in]
# Apply a generated clock to the output of the PLL
create_generated_clock -name pll_output \
-source [get_pins inst|altpll_component|pll|INCLK[0]] \
[get_pins inst|altpll_component|pll|CLK[0]]
# Apply a generated clock to the clk_out port
create_generated_clock -name clk_out \
-source [get_pins inst|altpll_component|pll|CLK[0]] \
[get_ports clk_out]
set_output_delay -clock clk_out 1.200 [get_ports data_out]
-reference_pin Option
The -reference_pin option is an Altera-specific extension to SDC that makes it easy to constrain source synchronous outputs. When you use the -reference_pin option with the set_input_delay/set_output_delay commands, you specify the input or output delay relative to a pin or port in the netlist.
The -reference_pin option automatically includes the clock latencies to the specified port or pin. For a source synchronous output, the output delay is relative to the output clock port. In the circuit in Figure 2, the latency from the clk_in port to the clk_out port is included by the -reference_pin option.
Figure 2. Source Synchronous Constraints with the -reference_pin Option
The following SDC commands constrain the output. No generated clock is necessary in this example, because the -reference_pin option includes the latency.
# Define the input clock
create_clock -period 10 -name clk_100 [get_ports clk_in]
# Apply a generated clock to the output of the PLL
create_generated_clock -name pll_output \
-source [get_pins inst|altpll_component|pll|INCLK[0]] \
[get_pins inst|altpll_component|pll|CLK[0]]
# Set the output delay with the -reference_pin option
set_output_delay -clock pll_output -reference_pin [get_ports clk_out] \
1.200 [get_ports data_out]
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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