TimeQuest Example: Basic SDC Example
The Synopsys Design Constraint (SDC) format provides a simple and easy method to constrain the simplest to the most complex designs. The following example provides the simplest SDC file content that constrains all clock (ports and pins), input I/O paths, and output I/O paths for a design. You can use the SDC file below as a template for any design. However, each design should contain a customized SDC file that individually constrains all clocks, input ports, and output ports.
# Global fMAX of 100 MHz
# All detected clocks will be constrained with a 100 MHz requirement
derive_clocks -period "100MHz"
# Automatically apply a generate clock on the output of phase-locked loops (PLLs)
# This command can be safely left in the SDC even if no PLLs exist in the design
derive_pll_clocks
# Constrain the input I/O path
set_max_delay -from [all_inputs] -to [all_registers] 1
set_min_delay -from [all_inputs] -to [all_registers] 2
# Constrain the output I/O path
set_max_delay -from [all_registers] -to [all_outputs] 3
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
|
Literature
> 
