TimeQuest Design Examples
These design examples show how to constrain different types of circuits for the TimeQuest timing analyzer.
Basic SDC Example
This example shows the simplest SDC file you can use that constrains all the clocks, input paths, and output paths in a design.
Multicycle Exceptions
This example shows how to make multicycle exceptions with SDC commands. It includes a simple circuit with a multicycle exception of 2.
Constraining Generated Clocks
You must constrain generated clocks in your design. See how to constrain a divide by 2 clock and a phase-locked loop (PLL) generated clock with this example.
Clock Multiplexer Examples
This example shows how to constrain multiplexed clocks in your design.
Constraining Maximum Skew
This example shows one way to constrain skew between a clock output port and the bits of a data bus driving off chip.
Basic Source Synchronous Output
This example shows two ways to constrain simple source synchronous outputs with a generated clock and with the Altera®-specific -reference_pin option.
Clock Enable Multicycle
This example shows how to apply a multicycle exception from a register feeding the clock enable pin of a register.
Custom Timing Report Script
This example shows how to use the Tcl Script File for customizing reports during compilation to generate custom reports in the Quartus II Compilation Report.
Reporting Multiple Operating Conditions
This example shows how to perform a multicorner analysis on your design with a Tcl script.
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