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Home > Support > Design Examples > Stratix/Stratix GX Print This Page Subscribe to Email Stratix & Stratix GX Design Examples The examples shown in Table 1 demonstrate various features of the Stratix® and Stratix GX device families using the Quartus® II design software. For more information about the different design entry methods, refer to the Help files in the Quartus II software. The Stratix and Stratix GX design examples are grouped by functionality. Select the design entry method icon to see the design example. Additional examples are available on the  Stratix Reference Designs page and  Stratix GX Reference Designs page. Table 1. Stratix & Stratix GX Design Examples for the Quartus II Software Memory Functions Design Entry Method Quad Data Rate (QDR) SRAM Controller Verilog HDL Examples for altufm Megafunction User Guide Quartus II Software Zero-Bus Turnaround (ZBT) SRAM Controller VHDL Buses & I/O Functions High-Speed Differential I/O Capability    Verilog HDL  Examples for altpll Megafunction User Guide Quartus II Software Examples for altremote_update Megafunction User Guide Quartus II Software Examples for altpll_reconfig Megafunction User Guide Quartus II Software Arithmetic Examples for altmult_add Megafunction User Guide Quartus II Software Examples for altfp_add_sub Megafunction User Guide Quartus II Software Storage Examples for lpm_rom Megafunction User Guide Quartus II Software Examples for lpm_shiftreg Megafunction User Guide Quartus II Software DSP Functions 12 x 9 Firm Multiplier Verilog HDL 12 x 12 Firm Multiplier Verilog HDL Fully Variable Coefficient Soft Multiplier Verilog HDL Hybrid Fixed Coefficient Soft Multiplier Verilog HDL Hybrid Variable Coefficient Soft Multiplier Verilog HDL Parallel Fixed Coefficient Soft Multiplier Verilog HDL Parallel Variable Coefficient Soft Multiplier Verilog HDL Semi-Parallel Fixed Coefficient Soft Multiplier Verilog HDL Semi-Parallel Variable Coefficient Soft Multiplier Verilog HDL Sum of Multiplication Fixed Coefficient Soft Multiplier Verilog HDL Sum of Multiplication Variable Coefficient Soft Multiplier Verilog HDL Discrete Cosine Transform (DCT) Verilog HDL Basic Finite Impulse Response (FIR) Filter Verilog HDL Time Domain Multiplexed FIR Filter Verilog HDL Polyphase Decimation FIR Filter Verilog HDL Polyphase Interpolation FIR Filter Verilog HDL Two-Dimensional FIR Filter Verilog HDL Basic Infinite Impulse Response (IIR) Filter Verilog HDL Butterworth IIR Filter Verilog HDL Magnitude Function Verilog HDL Design Examples Disclaimer These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera. Rate This Page

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