Mentor Graphics ModelSim Simulation Design Examples
Table 1 contains design examples demonstrating gate-level timing simulation of Altera® devices. Gate-level timing simulations are performed with Mentor Graphics® ModelSim® software to ensure that the post-synthesized or post-fit netlist passes the functional specifications.
The following icons indicate the entry mode(s) used in each example:
Altera hardware description language (AHDL)
VHDL
MAX+PLUS® II Graphic Editor
Verilog hardware description language (HDL)
Tool command language (Tcl)
Quartus® II development tool
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Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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