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Mentor Graphics ModelSim Simulation Design Examples

Table 1 contains design examples demonstrating gate-level timing simulation of Altera® devices. Gate-level timing simulations are performed with Mentor Graphics® ModelSim® software to ensure that the post-synthesized or post-fit netlist passes the functional specifications.

Table 1. Simulation Design Examples
Function Design Entry Method
PLL Gate-Level Timing Simulation R
Stratix® II GX Post-Fit Timing Simulation With ModelSim SE/PE Software R
Stratix II GX Post-Fit Timing Simulation With ModelSim-Altera Software R
Stratix II GX Post-Fit Timing Simulation With ModelSim SE/PE Software V
Stratix II GX Post-Fit Timing Simulation With ModelSim-Altera Software V
Stratix II Post-Fit Timing Simulation With ModelSim SE/PE Software R
Stratix II Post-Fit Timing Simulation With ModelSim-Altera Software R
Stratix II Post-Fit Timing Simulation With ModelSim SE/PE Software V
Stratix II Post-Fit Timing Simulation With ModelSim-Altera Software V
Simulation With NativeLink Feature in Quartus II Software R

The following icons indicate the entry mode(s) used in each example:

A Altera hardware description language (AHDL)
V VHDL
G MAX+PLUS® II Graphic Editor
R Verilog hardware description language (HDL)
T Tool command language (Tcl)
Q Quartus® II development tool

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Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

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