Graphic Editor: Cycle-Shared Dual-Port RAM (csdpram)
This example implements a dual-port RAM block with two inputs that are 4 bits wide and 16 words deep. You can change the width (LPM_WIDTH) and depth (LPM_WIDTHAD) parameters as needed for your design.
If you are using this function in a FLEX® 10K design, MAX+PLUS II can implement the RAM in embedded array blocks (EABs).
Download the Graphic Editor file used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
cycle.gdf
For more information on using this example in your project, go to:
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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