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DSP Design Examples

Table 1 contains digital signal processing (DSP) design examples for use in designs for Altera® devices. To see the design example, choose the corresponding icon in the Design Entry Method column.

Table 1. DSP Design Examples—Functions and Design Entry Methods
Function Design Entry Method
Upgrading an AtlanticTM Interface Design to an Avalon® Streaming Interface DesignNEW R
Achieving Unity Gain in Block Floating Point IFFT+FFT Pair Updated R
Coefficient Reload FIR Filter Updated Verilog hardware description language (HDL)
Polyphase Modulation With Aliasing for Digital Up-ConversionNEW Simulink model
Implementing OFDM Modulation and DemodulationNEW VHDL
Designing Digital Down Conversion Systems Using CIC and FIR FiltersUpdated Simulink model
Using CIC Decimation Filter With Multi-Channel Support Simulink model
CIC Interpolation Filter With Multi-Channel Data Support Simulink model
Deinterlacer Using Weave ModeUpdated Simulink model
Deinterlacer Using Bob ModeUpdated Simulink model
Gamma CorrectionUpdated Simulink model
YCbCr to RGB Color Space ConversionUpdated Simulink model
Image Frame Resizing Using ScalerUpdated Simulink model
Salt and Pepper Noise Removal Using 2D Median FilterUpdated Simulink model
Video Picture in Picture (PIP) Mixing Using Alpha Blending Mixer Updated Simulink model
Chroma Resampler Up-Conversion Updated Simulink model
2D Sharpening Finite Impulse Response (FIR) FilterUpdated Simulink model
Viterbi Tail-Biting Double-Pass Decoding (Packet Size = Traceback Length) Simulink model
Viterbi Tail-Biting Double-Pass Decoding (Packet Size = 2 Traceback Length) Simulink model
Viterbi Tail-Biting Triple-Pass Decoding (Packet Size = Traceback Length) Simulink model
Complex Finite Impulse Response (FIR) Filter Simulink model
Bit-Error Rate (BER) Performance Measurement of Viterbi Decoder Simulink model
Half-Band Filter Using Distributed Arithmetic Simulink model
Half-Band Filter Using Distributed Arithmetic & Time Domain Multiplexing (TDM) Simulink model
Half-Band Filter With Reloadable Coefficients Simulink model
Half-Band Filter Using DSP Blocks Simulink model
Fast Fourier Transform With 32K Points Transform Length Verilog hardware description language (HDL)
Complex Multiplier With Reloadable Coefficients Using Conventional Representation Simulink model
Complex Multiplier With Constant Coefficients Using Conventional Representation Simulink model
Complex Multiplier With Variable Coefficients Using Conventional Representation Simulink model
Complex Multiplier With Reloadable Coefficients Using Canonical Representation Simulink model
Complex Multiplier With Constant Coefficients Using Canonical Representation Simulink model
Complex Multiplier With Variable Coefficients Using Canonical Representation Simulink model
Viterbi Decoder With Node Synchronization VHDL
Signed Multiplier VHDL
Signed Multiplier With Registered I/O Verilog hardware description language (HDL)
Signed Multiply-Accumulator VHDL
Signed Multiply-Adder Verilog hardware description language (HDL)
Unsigned Multiplier Verilog hardware description language (HDL)
Unsigned Multiplier With Registered I/O VHDL
Unsigned Multiply-Accumulator Verilog hardware description language (HDL)
Unsigned Multiply-Adder VHDL
12 x 9 Firm Multiplier Verilog hardware description language (HDL)
12 x 12 Firm Multiplier Verilog hardware description language (HDL)
Fully Variable Coefficient Soft Multiplier Verilog hardware description language (HDL)
Hybrid Fixed Coefficient Soft Multiplier Verilog hardware description language (HDL)
Hybrid Variable Coefficient Soft Multiplier Verilog hardware description language (HDL)
Parallel Fixed Coefficient Soft Multiplier Verilog hardware description language (HDL)
Parallel Variable Coefficient Soft Multiplier Verilog hardware description language (HDL)
Semi-Parallel Fixed Coefficient Soft Multiplier Verilog hardware description language (HDL)
Semi-Parallel Variable Coefficient Soft Multiplier Verilog hardware description language (HDL)
Sum of Multiplication Fixed Coefficient Soft Multiplier

Verilog hardware description language (HDL)
Sum of Multiplication Variable Coefficient Soft Multiplier

Verilog hardware description language (HDL)
Discrete Cosine Transform (DCT)

Verilog hardware description language (HDL)
Basic FIR Filter

Verilog hardware description language (HDL)
Time Domain Multiplexed FIR Filter

Verilog hardware description language (HDL)
Polyphase Decimation FIR Filter

Verilog hardware description language (HDL)
Polyphase Interpolation FIR Filter

Verilog hardware description language (HDL)
Two-Dimensional FIR Filter

Verilog hardware description language (HDL)
Basic Infinite Impulse Response (IIR) Filter

Verilog hardware description language (HDL)
Butterworth IIR Filter

Verilog hardware description language (HDL)
Magnitude Function

Verilog hardware description language (HDL)

The following icons indicate the entry mode(s) used in each example:

Altera hardware description language (AHDL) Altera hardware description language (AHDL)
VHDL VHDL
MAX+PLUS® II graphic editor MAX+PLUS® II graphic editor
Verilog hardware description language (HDL) Verilog hardware description language (HDL)
Tool command language (Tcl) Tool command language (Tcl)
Quartus II development tool Quartus® II development tool
Simulink model Simulink model

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