DSP Builder: Complex Multiplier With Reloadable Coefficients Using Conventional Representation
This example describes an 18x18 signed complex multiplier design in DSP Builder. The complex multiplier is implemented using distributed arithmetic (DA) which is implemented using the M4K TriMatrix memory blocks. The coefficients are re-loadable. It uses the conventional representation requiring four multipliers, one adder, and one subtractor:
D = Dr + j*Di { Data }
C = Cr + j*Ci { Coefficient }
R = D*C = Rr + j*Ri { Result }
Rr = Dr*Cr – Di*Ci
Ri = Dr*Ci + Di*Cr
The coefficient is implemented as partial products in the M4K TriMatrix memory blocks. The M4K memory blocks are configured as dual-port RAMs and can store two sets of coefficients. To choose which coefficient set to use, set the coef_set bit appropriately.
The coefficient is also re-loadable while the multiplication operation takes place. It will automatically reload into the coefficient set which is not being used. To reload a new coefficient, assert the coef_reload bit and keep it asserted throughout the entire reload period. The partial product for the coefficient needs to be pre-computed. Refer to the compute_partial_product.m script for details.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the zip download include:
- complex_mult_BF_DA_reloadable_coef_MEM.mdl—DSP Builder design file implementing 18x18 complex multiplier with reloadable coefficients
- init.m—MATLAB script to initialize the sampling time, simulation time and coefficient value
- compute_partial_product.m—MATLAB script to calculate the partial products based on the constant coefficient value set in init.m. Two sets of partial products are calculated for each coefficient value: one for the most significant bit (MSB) segment and the other for the least significant bit (LSB) segment of the data
- complex_mul.m—MATLAB script to verify the simulation results in Simulink
Figure 1 shows the top-level diagram of the complex multiplier design example in DSP Builder.
Figure 1. Signed 18x18 Complex Multiplier Top-Level Diagram
View Full Size
Table 1 lists the ports and gives a description for each.
| Table 1. Signed Complex Multiplier Port Listing |
| Port Name |
Type |
Description |
DataInI[17:0], DataInQ[7:0] |
Input |
18-bit data inputs to complex multiplier unit |
| coef_real_msb[23:0], coef_real_lsb[23:0],
coef_imag_msb[23:0], coef_imag_lsb[23:0]
|
Input |
24-bit partial product inputs based on the coefficient to complex multiplier unit. Used during coefficient reloading. |
| coef_set |
Input |
The M4K memory block stores partital products for two sets of coefficients. This bit selects which set to use for the complex multiplication operation. |
| coef_reload |
Input |
Initiate reloading of coefficient into memory. It overwrites the coefficient set which is not being used (determined by coef_set bit) |
| ResI[36:0], ResQ[36:0] |
Output |
37-bit data output of complex multiplier unit |
Related Links
For more information on related features used in this design example in your project, go to:
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
|
Literature
> 
