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Verification and Board Level

Quartus® II software provides the most advanced CPLD, FPGA, and HardCopy® ASIC verification support available. In addition to integrating with all of the leading third-party verification tools and methodologies, Quartus II software provides:

  • TimeQuest Timing Analyzer
  • PowerPlay Power Analyzer
  • Chip Planner  
  • SignalTap® II Embedded Logic Analyzer
  • RTL Viewer/Technology Map Viewer
  • Third-Party Verification Support

TimeQuest Timing Analyzer

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  • ASIC-strength timing analysis tool
  • Native support for industry-standard Synopsys Design Constraint (SDC) format
  • Support for complex clocking schemes
  • Improved performance
  • Easier ASIC prototyping
  • Easy to use GUI

      View Video      Training      Support      Handbook (PDF)


PowerPlay Power Analyzer

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  • Automatically routes high-performance paths and then programs the non-performance paths as low power
  • Programmable Power Technology
  • Automatically powers down unused logic
  • Dramatically reduces overall power use

      View Video      Training      Support      Handbook (PDF)


Chip Planner

  • Helps you achieve timing closure faster and shorten verification time
  • Provides analysis and editing capabilities in an integrated floorplan
  • Allows you to make floorplan assignments, implement engineering change orders (ECOs), and perform power analysis

      Training      Support      Handbook (PDF)


SignalTap II Embedded Logic Analyzer

  • A system-level debugging tool that captures and displays real-time signal behavior
  • Gives you the ability to observe interactions between hardware and software in system designs
  • Supports the highest number of channels, sample depth, and clock speeds of any embedded logic analyzer
  • Graphical interface

      Training      Support      Handbook (PDF)


RTL Viewer/Technology Map Viewer

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  • Provides powerful ways to view your initial and fully mapped synthesis results during the debugging optimization, or constraint entry process
  • Allows you to view your initial synthesis results to determine whether you have created the desired logic

      View Video      Training      Support      Handbook (PDF)


Third-Party Verification Support

With Quartus II software, you can use a variety of third-party verification tools. Altera works closely with third-party companies that provide HDL simulation, design rule checker, static timing analysis, formal verification, and signal integrity analysis to ensure that you can take advantage of the latest verification tools and methodologies. A complete listing of third-party EDA vendors that support Altera® devices is available on the EDA Partners web page.

 

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