DSP Builder
 Digital signal processing (DSP) system design in Altera® programmable logic devices (PLDs) requires both high-level algorithm and HDL development tools. Altera's DSP Builder integrates these tools by combining the algorithm development, simulation, and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools with VHDL synthesis, simulation, and Altera development tools.
DSP Builder shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. The existing MATLAB functions and Simulink blocks can be combined with Altera DSP Builder blocks and Altera intellectual property (IP) MegaCore® functions to link system-level design and implementation with DSP algorithm development. DSP Builder allows system, algorithm, and hardware designers to share a common development platform.
You can use the blocks in DSP Builder to create a hardware implementation of a system modeled in Simulink in sampled time. DSP Builder contains bit-accurate and cycle-accurate Simulink blocks, which cover basic operations such as arithmetic or storage functions. You can integrate complex functions by using MegaCore functions in DSP Builder models.
Altera also offers the DSP Builder Advanced Blockset, a Simulink library that enables timing-driven Simulink synthesis.
Altera MegaCore functions are high-level, parameterized IP functions such as finite impulse response (FIR) filters and fast Fourier transforms (FFTs) that you can configure to meet system performance requirements quickly and easily. MegaCore functions support Altera's IP evaluation features, which allow you to verify the functionality and timing of a function prior to purchasing a license.
A full overview of DSP IP that works in conjunction with DSP Builder and the IP evaluation flow is available on the Altera IP MegaStoreTM website.
The DSP Builder Signal Compiler block reads Simulink Model Files (.mdl) that are built using DSP Builder and MegaCore blocks and generates VHDL files and tool command language (Tcl) scripts for synthesis, hardware implementation, and simulation. Figure 1 shows the DSP Builder design flow.
Figure 1. DSP Builder Design Flow
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