The Altera System FPGA Partners Program
System-Level Design
System-level design methodologies utilize higher level languages for system development and architecture exploration, and can lead to increased productivity, faster time-to-market, higher quality of results, and reduced risk. System-level design involves all tools along the electronic system level (ESL) development design flow, including design entry, behavioral modeling, synthesis, hardware/software co-design, and verification. These advanced design environments are ideally suited for high-capacity and high-performance FPGAs, such as Altera's Stratix® II and CycloneTM II devices.
However, to address the challenges of algorithmic and compute intensive designs found in advanced design environments such as digital signal processing (DSP), video and image processing, wireless communications, and encryption and decryption technologies, system-level design tools are required.
System FPGA Partner Program
The goal of the Altera® System FPGA Partner Program is to provide designers with all the tools and resources necessary for using FPGAs as a platform for system-level design. To accomplish this goal, the System FPGA Partner Program is driving the development, adoption, and interoperability of system-level design tools for FPGAs.
Altera and its partners are collaborating on creating greater interoperability between tools that enable software designers to accelerate their algorithms in FPGAs. As part of this process, Altera has opened up application programming interfaces (API) to both its SOPC Builder system-level development tools and the Nios® II integrated design environment (IDE).
System FPGA Methodologies
Altera and the other members of the System FPGA Partner Program strive to provide design flows that will ensure high-level language-based designs can ultimately be implemented in an FPGA, as shown in Figure 1.
Figure 1. System FPGA Design Flow
In the hardware flow, the system design tool optimizes algorithms and generates register transfer level (RTL) code or a gate-level netlist targeting the FPGA. The RTL code or gate-level netlist can then be imported to the Quartus® II software for place and route and FPGA programming. In the software flow, the system-level design tool generates SOPC Builder-ready components.
Altera and its System FPGA partners are developing hardware acceleration technologies, including the Nios II C-to-Hardware Acceleration Compiler.
Members of the System FPGA partner program include:
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