FPGA Design Flow
Compile Your First Design Using Quartus II Software
Understanding Altera FPGAs & CPLDs Design Flow
FPGA Design Flow CPLD Design Flow
Should I use Quartus II Web Edition software, Quartus II Subscription Edition software, or buy a development kit?
Altera offers both free Quartus II Web Edition software and Quartus II subscription software. To help you choose, view a detailed comparison file (PDF). You can also purchase a development kit which includes reference designs, IP cores, and a one-year, time limited evaluation license for Quartus II software.
What Quartus II software documentation and learning resources are available?
Table 1 lists some of the available software documentation and learning resources.
FPGA Design Flow
The Quartus II software now features unique advantages in design flow methodology, system design, timing-closure methodology, in-system verification technology, and third-party EDA support. Highlights of Quartus II software FPGA design flow features are provided below. Figure 1 shows a high-level example of some of the Quartus II software FPGA design flow options. Some steps can be performed in a different order than shown in Figure 1.
Figure 1. FPGA Design Flow
Design Entry and Synthesis Technology
Quartus® II design software delivers the highest productivity and performance for FPGAs, CPLDs, and HardCopy® ASICs and offers numerous design features to accelerate the design process:
- Various methods of Design Entry
- Scripting Support
- Incremental Compilation: Initial Setup
- SOPC Builder for system-level design
- MegaWizard® Plug-In manager to quickly and easily integrate a broad portfolio of intellectual property (IP) cores
- I/O pin assignment analysis to manage I/O pin use early
- Quartus II Integrated Synthesis
- 3rd Party Design Entry and Synthesis
- Basic Compilation Flow
More Info
Verification and Board Level Solution
Quartus® II software provides the most advanced CPLD, FPGA, and HardCopy® ASIC verification support available. In addition to integrating with all of the leading third-party verification tools and methodologies, Quartus II software provides:
- TimeQuest timing analyzer
- Integrated power analysis with the PowerPlay power analysis and optimization technology
- Chip planner (floorplan and chip editor)
- SignalTap® II embedded logic analyzer (supported by the incremental compilation feature to accelerate verification cycles)
- RTL Viewer / Technology Map Viewer
- Third Party Verification Support
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Optimization Tools
Quartus® II design software delivers the highest productivity and performance for FPGAs, CPLDs, and HardCopy® ASICs and offers numerous optimization features to enhance the design process:
- Incremental compilation: Optimization
- Physical synthesis optimization to tune designs for peak performance
- Design Space Explorer automatic design optimization script
- Optimization advisor
More Info
CPLD Design Flow
Easiest-to-Use Design Software for CPLDs
Altera’s Quartus® II Subscription Edition software and the no-cost Quartus II Web Edition software support MAX® II CPLDs with an easy-to-use and comprehensive design environment that can take CPLD design projects from start to finish (see Figure 2). Quartus II Subscription Edition and Quartus II Web Edition software also integrate seamlessly with all leading third-party synthesis and simulation tools.
Figure 2. Quartus II Software CPLD Design Flow
Quartus II Advantages for MAX+PLUS II Users
The Quartus II software is the highest performance and easiest-to-use software available for CPLD designs. With a built-in MAX+PLUS® II look-and-feel option, MAX+PLUS II software users can get the full benefits of the advanced features and performance of Quartus II software without having to learn a new interface. See Switching to Quartus II for MAX+PLUS II User.
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