Nios II C-to-Hardware Acceleration Compiler
The award winning Nios® II embedded processor C-to-Hardware (C2H) acceleration compiler is a tool that boosts the performance of your time-critical ANSI C functions by converting them into hardware accelerators in the FPGA.
Features
- Push-button acceleration of ANSI/ISO C code
- GHz performance with mW power consumption
- Tight integration with software design flow
- Direct connection of hardware accelerators to CPU's memory map
- Seamless support for pointers and arrays
- Efficient latency-aware scheduling and pipelining of memory transactions
Reducing Power Consumption by Adding Hardware
The rule of thumb in system design has been that adding hardware increases power demands. The careful use of hardware accelerators, however, inverts the rule: adding hardware can reduce power. By analyzing algorithms and implementing appropriate accelerators in programmable logic, you can increase your design’s performance while reducing power consumption in an embedded computing system.
Consider the case where an embedded designer wants the processor to execute code at 80 MHz while off-loading the heavy computational algorithms to hardware running at a lower clock frequency. In the test case, as shown in Table 1, the embedded processor running application code at 80 MHz with 5 hardware accelerators running at 1 MHz increased system performance by 6 times while still reducing system power by 55 percent.
| Table 1. Test Case Results |
| Case |
CPU Frequency (MHz) |
Accelerator Frequency (Frames/sec) |
System Performance
(Frames/sec) |
System Power (mWatts) |
| CPU Only |
80 MHz |
N/A |
Baseline |
Baseline |
| CPU + 5 Hardware Accelerators |
1 MHz |
1 MHz |
5X |
1/5X |
| CPU + 5 Hardware Accelerators |
80 MHz |
1 MHz |
6X |
1/2X |
Download the Reducing Power in Embedded Systems by Adding Hardware Accelerators article posted on Embedded.com
Dramatically Boost Embedded Software Performance
Hardware acceleration is a vital tool for software engineers who need to increase the performance of their embedded software applications. Hardware accelerators can take full advantage of the parallel processing structure of the FPGA to calculate more computations per clock cycle than general-purpose CPUs and deliver orders-of-magnitude increase in performance. See Table 2 for performance and area results for several common embedded computing algorithms.
| Table 2. User Application Results Example |
| Algorithm |
Speed Increase
(vs. Nios II CPU) |
System fMAX
(MHz) |
System Resource Increase (1) |
| Autocorrelation |
41.0x |
115 |
124% |
| Bit Allocation |
42.3x |
110 |
152% |
| Convolution Encoder |
13.3x |
95 |
133% |
| Fast Fourier Transform (FFT) |
15.0x |
85 |
208% |
| High Pass Filter |
42.9x |
110 |
181% |
| Matrix Rotate |
73.6x |
95 |
106% |
| RGB to CMYK |
41.5x |
120 |
84% |
| RGB to YIQ |
39.9x |
110 |
158% |
Note:
- System resource increase takes into account the logic element (LE) equivalent cost of on-chip resources such as multipliers and memories and shows the incremental cost of adding the accelerators and buffers.
This data shows that the Nios II C2H acceleration compiler can deliver considerable performance gains with minimal added cost and resources. For details on these example results, see the Automated Generation of Hardware Accelerators white paper (PDF).
Familiar Software Design Flow
Until now, offloading software to hardware accelerators was a manual task, benefiting only those developers with the tools, experience, and time required to create, test, and integrate register transfer level (RTL) blocks into their processor system. The Nios II C2H acceleration compiler automates the creation and integration of hardware accelerators, reducing development time from weeks to minutes.
If you've used the Eclipse-based Nios II integrated development environment (IDE) before, designing with the Nios II C2H acceleration compiler is even easier. All you need to do is:
- Profile your software code to identify performance-critical functions.
- Highlight the desired functions within the Nios II IDE and right-click to accelerate.
- Review the detailed C2H compiler report file to determine simple C code optimizations.
- Optimize and iterate until desired performance is met.
- Quickly meet your performance requirements and ship your product ahead of schedule.
The Nios II C2H acceleration compiler allows you to explore the design space more quickly and efficiently to optimize your application algorithms and to boost the performance over a software-only implementation. All you have to do is right-click to accelerate.
Ordering Information
You can order the Nios II C2H acceleration compiler today. See Table 2 for pricing and ordering information. A free evaluation is also available with the Nios II Embedded Design Suite (EDS) download. Contact your local Altera® representative for purchasing details.
| Table 2. Nios II C2H Acceleration Compiler Ordering Code and Pricing Information |
| Ordering Code |
Price |
Ordering Information |
| IPT-C2H-NIOS |
$2,995 |
In the United States and Canada, call 1-888-800-0631 or contact your local Altera representative. Outside North America, contact your local distributor.
Download a free evaluation of the Nios II C2H acceleration compiler included in the latest version of the Nios II Embedded Design Suite. |
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