Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 IP Products
   Embedded Processors
   Interfaces & Peripherals
          Peripherals
          PCI
          PCI Express
          Memory Controllers
          USB
          PCMCIA
          Ethernet
          I2C
          CAN
          PowerPC Bus
          HyperTransport
          RapidIO
          SerialLite
          Additional Functions
          Consortiums
          Literature
   DSP
   Communications
  
 About IP
      Designing with IP
      Evaluate and Download IP
      IP Certifications
      System Design
      Request IP
  
 IP Industry Partners
      About AMPP Program
      AMPP Core Partners
  

PCI Express

from PLDA

Request Free Evaluation



AMPP Approved
OpenCore Support
I-Test



Features

  • PCI Express Specification 1.1 and 2.0 compliant
  • x1, x4, x8 PCIe 1.1 and x1, x4 PCIe 2.0
  • Suitable for root complex, bridge, switch, and endpoint designs
  • Upstream and/or downstream mode for link initialization
  • Up to eight virtual channels (VC)
  • Optional backend interface on user's clock domain
  • Supports up to 4 KB data payload size
  • Supports all message, completion, memory, and I/O requests
  • Implements type 0 configuration space for endpoint designs
  • Implements type 1 configuration space for root, switch, and bridge designs
  • Up to six BARs plus expansion ROM available for endpoint
  • All I/O and memory windows implemented for root, switch, and bridge
  • All power management states and associated logic implemented
  • Supports legacy PCI Power Management
  • Support Express Card

PCI Express Product Selector Guide for Altera FPGAs

Table 1 shows the PCI Express Selector Guide for Altera® FPGAs.

Table 1. PCI Express Selector Guide for Altera FPGAs
End Point/
Rootport
Embedded PCIe PHY External PCIe PHY
Stratix GX Stratix II GX Arria GX Stratix Stratix II Stratix III Cyclone Cyclone II Cyclone III
Gen1
End Point
(x1)
Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark
End Point
(x4)
Check Mark

Check Mark

Check Mark

Check Mark

Check Mark

Check Mark

Check Mark

Check Mark

Check Mark

End Point
(x8)
  Check Mark     Check Mark Check Mark      
Rootport
(x1)
Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark
Rootport
(x4)
Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark Check Mark
Rootport
(x8)
  Check Mark              
Gen2
End Point
(x1)
  Check Mark              
End Point
(x4)
  Check Mark              

Deliverables

Core synthesis files (encrypted VHDL or Verilog for Quartus® II software)
Pre-compiled simulation libraries for ModelSim® IP Wizard:

  • Customization assistant
  • Constraint file generator
  • Active HDL supported upon request

Verification Environment

  • Testbench pre-compiled simulation libraries for ModelSim software 
  • VHDL/Verilog test scripts and compliance checklist

Software Resources

  • PCIe device driver: Windows, Linux
  • API source code
  • GUI applications with source code
  • Reference designs that are ready for hardware implementation
  • Documentation, including a users guide and design guide
  • One-year technical support and maintenance with free upgrades

Contact Information

For additional information, contact:

PLDA
Parc Club du Golf
Bat 11, rue Guillibert
13856 Aix-en-Provence Cedex 3, France
Telephone (USA): 1-866-513-0362 (toll free)
Telephone (International): +33-(0)-442-393-600
Fax (International): +33-(0)-442-394-902
Email: sales@plda.com 
URL: http://www.plda.com

Stratix, Arria, and Cyclone are trademarks of Altera Corporation.

  Please Give Us Feedback