Stratix IV FPGAs: The Lowest Power
High-End 40-nm FPGA
With the migration to low process nodes, Stratix® IV 40-nm FPGAs utilize the latest architecture innovations and process techniques to deliver the lowest power and the highest performance of any high-end FPGA.
Figure 1. Stratix IV FPGAs Deliver Less Power
Learn how your next-generation systems can take full advantage of the Stratix IV FPGA power conservation innovations:
Programmable Power Technology
Stratix IV FPGAs carry forward Programmable Power Technology, a proven Stratix III FPGA architecture, to minimize power and deliver highest performance where needed. Figure 2 shows how Programmable Power Technology works at the block level (logic, memory, or DSP) in Stratix IV FPGAs.
Figure 2. Standard FPGA Fabric vs. Stratix IV FPGA Fabric with Programmable Power Technology
- In standard FPGAs, all the logic blocks are designed to run at only one speed—the highest possible speed (as depicted by the yellow blocks)—resulting in excessively high power consumption.
- In an FPGA design, very few paths (on average only 20 percent) are timing critical. Using Programmable Power Technology in Stratix IV FPGAs, all logic blocks in the array, except those designated as timing critical, are set to low-power mode (as depicted by the blue blocks). With only the few logic blocks that are timing critical set to high-speed mode, Programmable Power Technology enables Stratix IV FPGAs to deliver the lowest power and the highest performance.
For any design, Quartus II software determines the slack available in each path of the circuit to automatically set the transistors (within blocks) to the appropriate mode—high performance or low power—by adjusting the back bias voltage of the transistor. This makes the transistor harder to turn on, thereby minimizing subthreshold leakage currents and unwanted static power. Figure 3, at a very high level, shows how Quartus II software controls the transistors to switch between high-performance and low-power mode.
Figure 3. Quartus II Software Minimizes Power and Maximizes Performance
For example, to set an NMOS transistor in the core of Stratix IV FPGAs to:
- Low-power mode, Quartus II software reduces the back bias voltage (making it more negative), which makes the transistor harder to turn on. This results in less leaky transistors and saves power in most of the design paths
- High-performance mode, Quartus II software increases the back bias voltage (making it less negative), which makes the transistor easier to turn on in the few timing-critical paths to help meet the design's specified timing constraints and deliver the maximum performance
For additional information on Programmable Power Technology, refer to the 40-nm Power Management and Advantages (PDF) white paper.
DDR3 and Dynamic On-Chip Termination (OCT)
Enabled by read/write leveling, Stratix IV FPGAs easily interface to DDR3 memories operating at 1.5 V, thereby reducing static power by 30 percent over DDR2 memories at 1.8 V.
Additionally, dynamic OCT further reduces static power by 1.02 W on a typical 72-bit DIMM (72 DQ and 18 DQS pins) by turning on and off series termination (RS) and parallel termination (RT ) dynamically during data transfer (see Figure 4).
Combining the effects of DDR3 voltage shrink and DOCT, Stratix IV FPGAs, on a typical 72-bit DIMM, lower parallel OCT static power by 65 percent at 1,067 Mbps when compared to a standard FPGA.
Figure 4. Dynamic OCT for Memory Interface
- During the write cycle, RS is turned on and RT is turned off to match the line impedance
- During the read cycle, RS is turned off and RT is turned on as the Stratix IV FPGA implements the far-end termination of the bus
For additional information on DDR3 and dynamic OCT, refer to the 40-nm Power Management and Advantages white paper (PDF).
Process and Circuit Technologies
Some of the technologies employed in Stratix IV FPGAs include multi-threshold transistors, variable gate-length transistors, low-k dielectric, triple-gate oxide (TGO), super-thin gate oxide, and strained silicon. For additional information on these process and circuit technologies, refer to the 40-nm Power Management and Advantages white paper (PDF).
PowerPlay Power Analysis and Optimization Tool
The PowerPlay power analysis and optimization tool in the Quartus II software uses accurate power models and information from your design implementation to keep the total power consumption of your designs to a minimum. To learn more, visit the Power Optimization for Stratix III FPGAs web page.
Related Links
|
Literature
> 
Next Steps