Stratix IV FPGA I/O Connectivity
Stratix® IV FPGA I/O pins have the system-level performance and flexibility required to communicate with a multitude of devices. Intellectual property (IP) cores, and software tools such as TimeQuest timing analyzer, simultaneous switching noise (SSN) estimator, and pin planner all aid in ease of use and rapid integration.
| Table 1. Stratix IV FPGA I/O Connectivity Overview |
| Feature |
Details |
| LVDS Support on All I/O Banks |
- Up to 132 full-duplex, 1.6-Gbps, true LVDS channels
(132 Tx + 132 Rx) on the side I/O banks
- Up to 288 lower speed pseudo-LVDS channels on top and bottom I/O banks
|
| DDR Support on All I/O Banks |
- Up to 31 hard I/O registers behind each DQ pin for best-in-class DDR support
- Up to 1067 Mbps (533 MHz) support on top and bottom I/O banks
- Up to 667 Mbps (333 MHz) support on side I/O banks
|
| Independent Banks |
- Up to 24 independent user I/O banks provide flexible and efficient pin usage
- Common bank structure for vertical migration
|
Differential Signaling
Stratix IV FPGA I/Os support high-performance, DC-coupled LVDS transmit and receive channels on the side I/O banks with additional lower speed LVDS support on the top and bottom banks. Every high-speed, side I/O LVDS pair has a hard dynamic phase alignment (DPA) block to eliminate clock-to-channel and channel-to-channel skew, as shown in Figure 1. Stratix IV FPGA high-speed LVDS I/O pins support interface standards such as SPI-4.2, SFI-4, SGMII, Utopia IV, 10 GbE XSBI, the RapidIO® standard, and SerialLite.
The Stratix IV FPGA high-speed LVDS feature supports the following:
- Hard DPA block with serializer/deserializer (SERDES) and clock-forwarding capability for soft-CDR
- Programmable pre-emphasis and Voltage Output Differential (VOD)
- Differential on-chip termination (OCT)
For more information on differential signaling see the High-Speed Differential I/O Interfaces with DPA in Stratix IV Devices (PDF) chapter of the Stratix IV Device Handbook.
Single-Ended I/O Support
The Stratix IV FPGA single-ended I/O feature supports the following:
- Programmable slew rate and drive strength
- Dynamic trace compensation (variable delay chains for board trace mismatch compensation on both input and output signals)
- Serial, parallel, and dynamic on-chip termination (OCT)
For more information about OCT see Termination Solutions in Stratix IV Devices.
Stratix IV FPGA I/O pins support single-ended I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI,
and PCI-X (see Table 2).
| Table 2. Stratix IV FPGA Differential and Single Ended I/O Support |
| I/O Standards |
Performance Target (1) |
Typical Application |
Comments |
| Differential I/O |
| LVDS |
1.6 Gbps |
Chip-to-chip |
OCT |
| Differential HSTL |
400 MHz |
Memory |
OCT |
| Differential SSTL |
400 MHz |
Memory |
OCT |
| LVPECL |
350 MHz |
General purpose |
Clock inputs only |
| Single-Ended I/O |
| 3.0-V/2.5-V/1.8-V LVTTL |
167 MHz |
General purpose |
Impedance matching |
| 3.0-V/2.5-V/1.8-V/1.5-V/1.2-V LVCMOS |
167 MHz |
General purpose |
Impedance matching |
| SSTL-2 Class I and II |
250 MHz |
Memory |
Serial and parallel OCT |
| SSTL-15 Class I and II |
533 MHz |
Memory |
Serial and parallel OCT |
| SSTL-18 Class I and II |
400 MHz |
Memory |
Serial and parallel OCT |
| 1.8-V/1.5V/1.2-V HSTL I and II |
400 MHz |
Memory |
Serial and parallel OCT |
| 3.0-V PCI |
66 MHz |
PC, embedded |
Impedance matching |
| 3.0-V PCI-X 1.0 |
133 MHz |
PC, embedded |
Impedance matching |
Note:
- Pending characterization
For more information on I/O standards see the I/O Interfaces (PDF) chapter of the Stratix IV Device Handbook.
High-Speed External Memory Interfaces
Stratix IV FPGA I/O pins support existing and emerging external memory standards such as DDR, DDR2, DDR3, QDRII, QDRII+ and RLDRAMII at frequencies up to 400 MHz (see Table 3). A self-calibrating datapath takes advantage of the new I/O structure, dynamically adjusting itself to always provide the highest reliable frequency of operation across process, voltage, and temperature.
The Stratix IV FPGA external memory interfaces feature supports the following:
- SDR and half data rate (HDR–half the frequency and twice the data width of SDR) input and output options
- HDR block with alignment and synchronization
- De-skew, read/write leveling and clock-domain crossing functionality
| Table 3. Stratix IV FPGA External Memory Interface Performance (1) |
| Memory Standard |
I/O Standard |
Maximum Clock Speed |
Maximum Data Rate |
| DDR SDRAM |
SSTL-2 |
200 |
400 Mbps |
| DDR2 SDRAM |
SSTL-1.8 |
400 |
800 Mbps |
| DDR3 |
SSTL-1.5 |
533 |
1067 Mbps |
| QDRII |
1.8v / 1.5v HSTL |
350 |
1400 Mbps |
| QDRII + |
1.8v / 1.5v HSTL |
350 |
1400 Mbps |
| RLDRAMII |
1.8v HSTL |
400 |
800 Mbps |
Note:
- Pending characterization
For more information on external memory interfaces on Stratix IV FPGAs, see Altera's External Memory Solution Center and the External Memory Interfaces in Stratix IV Devices (PDF) chapter of the Stratix IV Device Handbook.
Signal Integrity
Stratix IV FPGA I/O banks deliver best-in-class signal integrity, low SSN, and superior eye quality through many chip-level and package-level enhancements.
The Stratix IV FPGA signal integrity I/O feature supports the following:
- 8:1:1 User I/O to power/ground ratio
- Optimized signal return paths
- Staggered output delay control
- Optimized on-die and on-package decoupling
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