Military Risk and Productivity
Program Risk and the Jump to 40-nm Technology
As silicon manufacturing moves ahead to the newest technology node, Altera and FPGA designers made a very careful risk decision. The Altera® FPGA design team executed a careful risk management program in shrinking the Stratix® III architecture to 40 nm, while convincing designers that the added functionality and capability justified the risk of overcomplicating the design process and silicon delivery schedule.
Moving the 40-nm process technology half-node, Altera applied a measured risk management process in manufacturing design and production. We executed a rigorous multi-stage test chip program, with emphasis on producible transceiver technology. Details of our 40-nm development schedule, as well as our risk management profile, are available upon request to military customers.
Military User Requirements
With the introduction of Stratix IV FPGAs, the design domains (see Figure 1) of military electronics that can be addressed with programmable logic devices (PLDs) are growing. Functions that were once restricted to ASIC designs or microprocessor systems now benefit from the shorter design cycle times and simpler hardware verification processes of an FPGA.
Figure 1. Defense System Design Domains
The effect of larger designs and greater potential for system-on-a-chip (SoC) integration places more emphasis on tool flow and intellectual property (IP) reuse. This is especially true given the more difficult verification and rigorous test requirements of military electronics systems.
The relationship between military user requirements and commercially available technology is not accidental. A growing number of national militaries are being equipped entirely with commercial off-the-shelf (COTS) equipment. Likewise, the US Military is continually being challenged to leverage commercially available technology into battlefield settings. Today’s soldiers, familiar with handheld and wireless technology back home, demand similar soldier-to-soldier connectivity in the field.
While the number of technical requirements that must be considered by systems engineers cannot be easily summarized, there are four large initiatives in military electronics technology that are addressed by the larger class of new FPGAs. These are reductions in size, weight, and power (SWaP), common data bus standards ("open systems"), design re-use, and anti-tamper technologies.
The simplest approach to reducing SWaP is integrating many subsystems into a single chip. While this can be enabled through robust systems engineering processes and workflow controls, it increases the importance of open systems design and anti-tamper technologies for FPGAs. To see improvements in efficiency in new, larger SoC designs, design re-use must be a fundamental part of systems design flow.
IP Reuse, Open Systems, and DO-254 Certification
Military electronics face new challenges that impact the FPGA design flow. Among these are the re-use of IP between programs, the compliance of that IP to open systems interface standards, and the flight safety certification of this IP to meet new DoD regulations. See Figure 2.
Figure 2. IP Reuse and Integration
The Altera design flow makes standard interface IP available throughout the design entry process. This includes the high-speed Serial RapidIO® standard, both soft and hard PCI Express cores, and 10-Gigabit Ethernet cores optimized for Altera’s high-speed transceiver technology. For your own internally developed IP cores, encapsulation of these cores in Altera’s SOPC Builder is a simple process allowing for easy archival and retrieval of important re-usable logic blocks.
In addition, DO-254 certification support is available for IP and synthesized designs through a partner network of design verification tools and documentation support. This includes documentation for the Nios® II embedded processor, currently being used in DO-254 subject avionics systems.
Time to Focus on Design Flow
While there are plenty of reasons to focus on the newest high-density and high-speed transceiver capabilities of Stratix IV GX FPGAs, cost-conscious military customers will want to focus their efforts on the impact of design flow technology on their organization. Design time productivity for large programmable devices, to include verification, debug, and compile times, is a significant schedule risk in defense programs. As a result, Altera has invested significantly in compile-time improvements, multiprocessor synthesis support, incremental compile to include team-based "bottoms up" design, and SOPC Builder for fast system bus generation.
Studies for device selection traditionally trade cost versus performance. Once FPGAs are capable of containing enough of an electronic system’s functions, the number one system cost driver is tool flow efficiency. While this is not simple to assess or measure, selecting the right tool flow for defense electronics design is paramount for cost competitiveness and efficient organizational operation.
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