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Home > Products > Devices > Stratix III (L and E) Print This Page Subscribe to Email Stratix III Device Family—The Lowest Power High-Performance 65-nm FPGAs Highest Performance Highest Density Family Overview Enhanced DSP Capabilities Programmable Power Technology OpenCores Validate Stratix III Advantages Getting started on that next-generation system design? Imagine how much smoother the task would be with an FPGA that gives you the capabilities to implement any design with high productivity and low risk. With Altera’s Stratix® III family of high-end FPGAs, you get the world's highest performance and highest density 65-nm devices combined with the lowest possible power consumption. Stratix III FPGAs provide the high-performance and high-integration capabilities needed for next-generation basestations, network infrastructure, and advanced imaging equipment. What's more, the performance, utilization and compilation advantages of Stratix III FPGAs actually increase with design size: OpenCore designs validate increased Stratix III FPGA advantages with increasing design size With Altera's innovative custom logic solutions, you get the devices you want with the features you want when you want them. You also get the collaboration and support you need to design your next-generation systems with confidence. Figure 1. Stratix III FPGAs Building on the Stratix II Architecture Lowest Power High-End 65-nm FPGAs To design the Stratix III FPGA family, Altera's product planners began with the Stratix II FPGA architecture. Then, in collaboration with the top technologists from over 50 of Altera's major customers, they defined, designed, and developed the most advanced FPGA architecture for next-generation systems. As a result, Stratix III 65-nm FPGAs incorporate features to combine high performance with the lowest possible static and dynamic power consumption—up to 50 percent lower than previous generation high-end FPGAs, including: Programmable Power Technology Selectable core voltage (0.9 V or 1.1 V) Process and circuit technologies Quartus® II PowerPlay power analysis and power optimization technology Stratix III FPGAs are engineered for high-speed core performance, coupled with high-speed I/O and the best signal integrity in the industry. For example, they are the only 65-nm FPGAs capable of implementing DDR3 at 533 MHz and to offer LVDS performance up to 1.6 Gbps. This increase in performance is achieved by the implementation of: Enhanced digital signal processing (DSP) blocks for easy implementation of signal processing algorithms Optimized internal memory for enhanced signal integrity memory interfaces High-performance external memory interfaces Enhanced routing architecture I/O flexibility to support the latest external memory standards Best Price/Performance Options To give you the best price/performance solution for your design applications, Altera's Stratix III FPGAs are offered in two application-optimized variants: Stratix III L devices focus on logic-rich applications Stratix III E devices focus on DSP-rich and memory-rich applications HardCopy® ASICs provide a no-risk design handoff from Stratix III high-density logic to low-cost, high-performance, high-volume production. Advanced Process Technology Altera and long-standing fabrication partner the Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), have been working on 65-nm process technologies since 2003. Since then, Altera has developed multiple test chips as part of a rigorous program to ensure that Stratix III FPGAs are on the latest 65-nm technology, and continue to be successfully delivered in volume and on schedule. Exceed Performance and Finish Faster Altera’s Quartus II software gives you the development and productivity tools you need to complete development faster and ensure you have the performance, power, and signal integrity needed to meet or exceed your design requirements. TimeQuest Timing Analyzer—supports industry-standard Synopsys Design Constraints (SDC)-based timing analysis methodology to complete timing closure quickly Incremental Compilation—supports team-based design, providing faster compilation for design iterations while preserving performance PowerPlay Power Analysis and Optimization Technology—provides automated power optimization to manage power from design concept through implementation Four-Stage Signal Integrity Analysis—provides optimal design performance ASIC Co-Design—supports seamless migration between Stratix III FPGAs and HardCopy ASICs Related Links Stratix III device family overview View the Stratix III webcasts Designing Stratix III FPGAs with Quartus II software Stratix III Devices: Features and Capabilities (Online Training) Find out how Stratix III FPGAs will reduce your power consumption Rate This Page

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