External Memory Interfaces in Stratix II Devices
To complement the high-performance logic architecture of its Stratix® II FPGAs, Altera provides on-chip access to high-bandwidth memory via the proven TriMatrix memory structure and access to off-chip memory through dedicated memory interface circuitry supporting the latest high-performance memory interfaces. Building on the success of the Stratix device family, Altera works with leading vendors to ensure users can connect the very latest memory devices to Stratix II FPGAs. Using the advanced device features of Stratix II devices and customizable intellectual property (IP), you can quickly and easily integrate a wide range of high-density memory devices into complex system designs without compromising performance.
The latest high-performance product architectures create an ever-increasing demand for total system memory bandwidth, pushing I/O bandwidth and processing power requirements to new levels. In response to these memory-intensive applications, memory device makers have developed larger, more feature-rich devices that are capable of high-speed data transfer. As applications continue to require specialized memory capabilities and features, memory types proliferate. Each type of memory is focused on specific requirements such as speed, cost, or size.
To address these requirements, Stratix II devices are designed to support a wide variety of cutting-edge memory interfaces (summarized in Table 1) either as discrete devices or as standard dual in-line memory modules (DIMMs). More information about these memory device types and Altera support for them is available on the Memory System Solutions web page.
| Table 1. High-Performance External Memory Interface Support in Stratix II Devices |
| Memory Technology |
I/O Standard |
Maximum Bus Width |
Maximum Clock Speed |
| Single Data Rate (SDR) SDRAM |
LVTTL |
72 bits |
200 MHz |
| Double Data Rate (DDR) SDRAM |
SSTL-2 Class I, II |
72 bits |
200 MHz |
| DDR2 SDRAM (1), (2) |
SSTL-18 Class I, II |
72 bits |
333 MHz |
| RLDRAM II (2) |
1.8-V HSTL Class I, II
1.5-V HSTL Class I, II |
36 bits |
300 MHz |
| Quad Data Rate II (QDRII) SRAM (2) |
1.8-V HSTL Class I, II
1.5-V HSTL Class I, II |
36 bits |
250 MHz |
Notes to Table 1:
- Contact Altera for the 667 Mbps solution. Refer to the DDR2 controller IP page for the 533 Mbps solution.
- Shows improvement over Stratix FPGAs.
Optimized for Performance
Stratix II devices have been designed for reliable data transfer to and from external memory devices at high speed. The Stratix II FPGA family capitalizes on the fact that memory clock speeds are steadily increasing. The key to high-speed interfacing is including dedicated I/O features to ensure that all timing requirements are satisfied and performance is maximized with minimum design effort. These features are outlined in Table 2.
| Table 2. Stratix II Device I/O Features |
| Feature |
Detail |
Benefit |
| Dedicated Data Strobe DQS Circuitry |
- Shifts DQS signal for optimized clock and data alignment during read cycles without using external PCB trace delays
- Minimizes clock skew between strobe DQS and data DQ signals through dedicated clock trees
- Has improved granularity of delay control over Stratix devices
|
- Ensures high-speed DDR memory timing requirements can be met reliably while saving PCB cost
|
| Dedicated Delay-Locked Loops (DLLs) |
- Provides two DLLs (one at the top and one at the bottom of the device) to control the DQS delays
|
- Provides full process-, voltage‑, and temperature- (PVT) compensated-accurate DDR timing without burning user resources
|
| Multi-Register I/O Elements (IOEs) |
- Maximizes performance with input, output, and output enable (OE) registers
- Separate registers for high and low edge of clock
|
- Provides high-performance DDR I/O functions
|
| Soft Interface Core |
- Exposes the DLL and DQS delay setting bus to fine-tune run time of the DQS read delay
- Enables easier resynchronization with the core with the delayed DQS signal
|
- Provides an easy interface to the advanced memory support features
- Provides possibility of run-time tuning of DQS delays to ensure performance is optimized for all systems
|
| Programmable Input Delays |
- Can delay input DQ signals so that they are in the center of a timing window
|
- Meets input timing requirements for various memory devices
|
Figure 1 shows the Stratix II FPGA IOE and its DDR functionality.
Figure 1. Stratix II Device I/O Circuitry
In addition to the I/O interface-specific features, Altera® Stratix II devices maximize memory interface performance using general-purpose programmable logic features as outlined in Table 3.
| Table 3. Stratix II Device Features Benefiting External Interface Performance |
| Feature |
Detail |
Benefit |
| Phase-Locked Loops (PLLs) |
- Synthesizes high-speed clock and data strobe signals
- Contains multiple outputs with fine phase control
|
- Performs precise phase shifting for clock and data alignment—enabling high-speed operation
|
| Advanced Clock Networks |
- Provides global and localized clock resources in the Stratix II device
|
- Provides freedom to implement different clock domains (necessary for high-speed interfaces)
|
| Multiple I/O Banks |
- Provides eight separate I/O banks with I/O standard support including:
- LVTTL
- 1.5-V/1.8-V HSTL
- SSTL-2
- SSTL-18
|
- Supports multiple I/O standards and memory types in a single chip
|
IP Optimized for Stratix II Devices
Altera offers fully customizable intellectual property (IP) megafunction controller cores developed and tested by Altera and Altera Megafunction Partners Program (AMPPSM) partners on the IP MegaStoreTM website. Altera also offers several memory controller design examples for users designing their own custom memory interfaces. These megafunctions allow you to quickly and easily incorporate the latest semiconductor memory technologies into your Stratix II designs using an intuitive graphical user interface (GUI) from within the Quartus® II software. This process automatically configures all of the dedicated external memory support features of Stratix II devices. Where time to market is critical, memory controller IP enables you to focus on your products’ functionality.
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