Stratix II GX Physical Coding Sub-Layer
The Stratix® II GX transceiver FPGAs include specific digital functionality to deliver physical coding sub-layer compliance for a number of key protocols used in backplane, line card, and chip-to-chip applications. The blocks are optimized for enhanced protocol support, reducing the amount of resources required in the FPGA to implement the physical layer of the protocol, while maintaining a low-power solution. The blocks, when combined with specific intellectual property (IP) and reference designs, can provide a complete protocol solution, both simplifying potentially complex designs and reducing project risk. Table 1 shows the key protocols supported by Stratix II GX transceiver FPGAs.
Note:
- Data rate supported using oversampling
Physical Coding Sublayer Block
The physical coding sublayer (PCS) block simplifies protocol support by including specific hard logic within the transceiver. Figure 1 shows a block implementation of the Stratix II GX PCS architecture.
Figure 1. Stratix II GX PCS Architecture
View Full Image
The Stratix II GX PCS provides key features to deliver protocol compliance within the transceiver block. In addition, dedicated state machines are included to support the PCI Express, GbE, and XAUI protocols. The state machines both configure and control the various PCS sub-blocks to support the specified protocol, further simplifying implementation. Tables 2 and 3 show PCS support by protocol.
| Table 2. PCS Implementation by Protocol (8b/10b Encoding) |
| Required PCS Functions |
PCI Express
(Gen. 1) |
GbE |
XAUI |
Serial RapidIO |
SerialLite II |
| Data Rates (Gbps) |
2.5 |
1.25 |
3.125 |
3.125 |
0.622 – 6.375 |
| Channel Bonding |
1, 4, 8 |
1 |
4 |
1, 4 |
up to x16 |
| Possible Reference Clock Values (MHz) |
100 |
125 |
156.25 |
156.25 |
62.2-622.08 |
| FPGA Bus Width (bits) |
8 or 16 |
8 |
16 |
16 |
8, 10, 16, 32 |
| Dedicated Sync State Machine |
 |
|
|
|
|
| Word Align |
|
|
|
|
|
| Rate Match |
|
|
|
|
|
| Byte Serialize/Deserialize |
|
|
|
|
|
| Phase Comp FIFO Buffer |
|
|
|
|
|
| Byte Re-Ordering |
|
|
|
|
|
| Single Bit Slip |
|
|
|
|
|
| Special Interface |
PIPE-1.0 |
GMII Like (2) |
XGMII Like (3) |
|
|
| Table 3. PCS Implementation by Protocol (Scrambled Encoding) |
| Required PCS Functions |
CEI-6G |
SDH/SONET |
Scrambled Backplane |
SD-SDI |
HD-SDI |
| Data Rates (Gbps) |
6.375 |
0.622 |
2.488 |
0.270 (1) |
1.485 |
| Channel Bonding |
1 |
1 |
1 |
1 |
1 |
| Possible Reference Clock Values (MHz) |
155.52 - 622.08 |
62.2, 311.04 |
77.76, 155.52, 311.04, 622.08 |
67.5 |
74.25 |
| FPBA Bus Width (bits) |
32 |
8 |
16 |
10 |
10 |
| Word Align |
|
|
|
|
|
| Rate Match |
|
|
|
|
|
| Byte Serialize/Deserialize |
|
|
|
|
|
| Phase Comp FIFO Buffer |
|
|
|
|
|
| Byte Re-Ordering |
|
|
|
|
|
| Single Bit Slip |
|
|
|
|
|
Notes to Tables 2 and 3:
- Data rate achieved by oversampling
- GMII support for Gigabit Ethernet only
- XGMII has SDR instead of DDR interface
Each block within the transceiver is highly configurable to support both industry standard and customer proprietary protocols. Transceiver implementation is simplified within the Quartus® II development tool. The tool automatically configures the transceiver PCS block, to the support the selected protocol, speeding up implementation and reducing design risk. The development tools also provide basic configuration modes for proprietary and non-standard protocols.
Built-In Self Test (BIST)
The BIST provides a powerful set of diagnostic capabilities to the transceiver. It includes a pattern generator and checker for pseudo-random binary sequence (PRBS) and others. The BIST also features four loopback configurations that can be used for system diagnostics, allowing interrogation of the physical media attachment (PMA), the PCS, or both the PMA and PCS layers of the transceiver into the FPGA.
Related Links
|
Literature
> 
