MAX 3000A CPLD Family Overview
Altera's MAX® 3000A CPLD family is manufactured on a cost-optimized 0.30-µm, four-layer-metal process, and ranges in density from 32 to 512 macrocells. Available in both commercial and industrial grades, in popular speed grades and packages, the 3.3-V MAX 3000A CPLD family is ideal for cost-sensitive, high-volume applications.
Table 1 lists the MAX 3000A device offerings.
| Table 1. MAX 3000A Device Overview (3.3 V) |
| Feature |
Device |
| EPM3032A |
EPM3064A |
EPM3128A |
EPM3256A |
EPM3512A |
| Usable Gates |
600 |
1,250 |
2,500 |
5,000 |
10,000 |
| Macrocells |
32 |
64 |
128 |
256 |
512 |
| Maximum User I/O Pins |
34 |
66 |
96 |
158 |
208 |
| tPD (ns) (1) |
4.5 |
4.5 |
5.0 |
7.5 |
7.5 |
| tSU (ns) (2) |
2.9 |
2.8 |
3.3 |
5.2 |
5.6 |
| tCO1 (ns) (3) |
3.0 |
3.1 |
3.4 |
4.8 |
4.7 |
| fCNT (MHz) (4) |
227.3 |
222.2 |
192.3 |
126.6 |
116.3 |
| Device Availability |
Buy Now |
Buy Now |
Buy Now |
Buy Now |
Buy Now |
| Package |
I/O Pins |
| 44-Pin PLCC (5) |
34 |
34 |
|
|
|
| 44-Pin TQFP (6) |
34 |
34 |
|
|
|
| 100-Pin TQFP |
|
66 |
80 |
|
|
| 144-Pin TQFP |
|
|
96 |
116 |
|
| 208-Pin PQFP (7) |
|
|
|
158 |
172 |
| 256-Pin FineLine BGA® (8) |
|
|
98 |
161 |
208 |
Notes:
- tPD (ns) = Data path delay from input to non-registered output
- tSU (ns) = Global clock setup time
- tCO1 (ns) = Delay from global clock to output
- fCNT (ns) = 16-bit counter internal global clock frequency
- PLCC = Plastic J-lead chip carrier
- TQFP = Thin plastic quad flat pack
- PQFP = Plastic quad flat pack
- BGA = Ball-grid array
To sample or to purchase MAX 3000A devices, contact your nearest Altera® sales representative or distributor.
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