FLEX 6000 Device Family
OptiFLEX Architecture Redefines Programmable Logic Efficiency
The SRAM-based FLEX® 6000 family features OptiFLEX® architecture, which is built on a 5.0-V, 0.30-micron or a 5.0-V, 0.42-micron, triple-layer metal CMOS process.
Figure 1 shows the FLEX 6000 architecture.
Figure 1. FLEX 6000 Architecture
The logic array contains logic array blocks (LABs) composed of 10 logic elements (LEs) that communicate through a fully populated local interconnect structure. The FLEX 6000 LAB has been enhanced to support LAB interleaving, an innovative feature that gives any LE the flexibility to access the local interconnect of its own LAB as well as adjacent LABs (see Figure 2). LAB interleaving leverages the inherent speed and flexibility of local resources, while optimizing global row and column resource utilization within the FLEX architecture. Each LE contains a four-input look-up table (LUT), a programmable register, and dedicated paths for carry and cascade functions.
Figure 2. Interleaved LABs
The logic array is routed through the Altera patented FastTrack™ Interconnect routing structure, a series of fast, continuous row and column channels that run the entire length and width of the device, as shown in Figure 3. Each FastTrack row and column feeds multiple I/O elements (IOEs), which provide programmable slew-rate and individual tri-state output enable control for each pin.
Figure 3. FastTrack Interconnect
The FLEX 6000 family also supports FastFLEX™ I/O, a feature that provides a direct path from the LE to the I/O pin for fast clock-to-output timing. Figure 4 details the FastFLEX I/O.
Figure 4. FastFLEX I/O
Maximum Die Size Reduction with µPitch Bond Pad Technology
To support costs competitive with gate arrays, Altera engineers combined the OptiFLEX architecture with an advanced 3.2-mil bond pad pitch. Figure 5 details the µPitch technology.
Figure 5. µPitch Technology
This combination of architecture optimization and µPitch bond pad technology maximizes silicon efficiency, producing a FLEX 6000 die size that is competitive with that of gate arrays. Figure 6 compares the relative die sizes of a gate array and a FLEX 6000 device.
Figure 6. Relative Die Sizes of a Gate Array & a FLEX 6000 Device
Because of their OptiFLEX architecture, FLEX 6000 devices can offer higher performance than FPGAs at a significantly lower price.
Table 1 summarizes FLEX 6000 performance in some typical applications.
| Table 1: FLEX 6000 Performance |
| Benchmark |
LEs Used |
-1 Speed Grade |
-2 Speed Grade |
-3 Speed Grade |
| 16-bit loadable counter |
16 |
172 MHz |
153 MHz |
133 MHz |
| 16-bit accumulator |
16 |
172 MHz |
153 MHz |
133 MHz |
| 24-bit accumulator |
24 |
136 MHz |
123 MHz |
108 MHz |
| 16-to-1 multiplexer |
10 |
12.1 ns |
13.4 ns |
16.6 ns |
| 16 x 16 multiplier, 4-stage pipeline |
592 |
84 MHz |
67 MHz |
58 MHz |
| 8-bit, 16-tap parallel finite impulse response (FIR) filter |
599 |
94 MSPS |
80 MSPS |
72 MSPS |
| 8-bit, 512 point fast Fourier transform (FFT) |
1,166 |
75 µS
63 MHz |
89 µS
53 MHz |
109 µS
43 MHhz |
| a16450 universal asynchronous receiver/transmitter (UART) |
478 |
36 MHz |
30 MHz |
25 MHz |
| PCI bus target with one wait state |
398 |
56 MHz |
49 MHz |
42 MHz |
Flexible Pin Migration
As shown in the overview, FLEX 6000 devices are available in a range of package types, including the space-saving 1.0-mm FineLine BGA® packages. Each FLEX 6000 device is footprint-compatible with other devices in the same package, maximizing productivity by supporting concurrent HDL design and board layout. Designs that grow beyond the capacity of a device can be easily migrated to a larger device without requiring a board re-spin. This feature also enables the designer to use a larger device for easy prototyping, while maintaining the flexibility to optimize the production design to fit pin-compatible devices that are smaller and lower-cost.
Efficient Software Development
To help you quickly design with FLEX 6000 devices, Altera offers the most powerful, flexible, and easy-to-use development tools in the industry. The Quartus® II development software leverages the efficiency of the OptiFLEX architecture by offering the industry's most automatic and sophisticated placement and routing algorithms. This combination of efficient device architecture and intelligent software algorithms allows the system designer to achieve desired place and route results within a matter of minutes while using a high percentage of the device's resources.
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