Cyclone Interface & Protocol Support
Cyclone™ devices support serial, bus, and network interfaces such as PCI, access to fast external memory devices, and a wide range of communications protocols including Ethernet protocols. These interfaces and protocols are commonly used in many consumer, industrial, and communications applications. Altera offers a variety of intellectual property (IP) cores for these protocols that are optimized for the Cyclone FPGA architecture.
PCI
PCI is a standard bus interface used as an interconnect between integrated components, peripheral add-in boards, and processor and memory systems. Cyclone devices are compliant with the 3.3-V PCI Local Bus Specification Revision 2.2, supporting the 32-bit PCI bus for performance up to 66 MHz. The I/O elements in Cyclone devices are specifically designed to meet the strict PCI set-up and hold time requirements. To provide maximum flexibility, each input signal can go through two separate delay paths feeding different areas of the device (Figure 1).
Figure 1. Cyclone Device I/O Element
SDRAM & FCRAM Interface
SDRAM and fast-cycle random access memory (FCRAM) are used broadly in applications from PCs and consumer electronics to communications and networking for data storage. Cyclone devices are designed to communicate with single data rate (SDR) and double data rate (DDR) SDRAM, as well as DDR FCRAM devices through a dedicated interface that ensures fast, reliable data transfer at up to 266 Mbps. Details are available on the External Memory Interfaces in Cyclone Devices web page.
10/100 & Gigabit Ethernet
Ethernet is the most widely used local area network (LAN) access method and is defined by the IEEE 802.3 standard. Cyclone devices can be used to implement the Ethernet media access controller (MAC) and can be interfaced with the physical layer (PHY) devices at a maximum bandwidth of 10 Mbps, 100 Mbps, or 1 Gbps. Together with Cyclone device-optimized IP cores, designers can integrate an Ethernet MAC function into a Cyclone device in minutes.
Serial Bus Interfaces
Cyclone devices support a variety of serial bus interfaces such as serial peripheral interface (SPI), inter-integrated circuit (I2C), IEEE 1394 standard, and universal serial bus (USB), as shown in Table 1.
| Table 1. Serial Bus Interface Support in Cyclone Devices |
| Protocol |
SPI |
I2C |
IEEE 1394 |
USB 2.0 |
| Maximum Bandwidth (Mbps) (1) |
1 |
3.4 |
400 |
480 |
Note:
(1) Maximum bandwidth is equal to or greater than the data rate.
The SPI and I2C standards can be implemented in Cyclone devices to provide low-speed communication links between integrated circuits, processors, and peripherals. The IEEE 1394 and USB standards provide connections between processors, computers, and other devices. Cyclone devices can be used to implement the bus controllers and interface with the PHY devices. All these serial bus interfaces are typically used in price-sensitive consumer products. The Cyclone device family provides an ideal low-cost solution for implementing the standards and custom functions for these applications.
Communications Protocols
Cyclone devices support various communication protocols including E1, E3, T1, T3, and SONET/SDH (Table 2).
| Table 2. Communications Protocol Support in Cyclone Devices |
| Protocol |
E1 |
E3 |
T1 |
T3 |
OC-1/ STM-0 |
OC-3/ STM-1 |
OC-12/ STM-4 |
OC-48/ STM-16 |
| Maximum Bandwidth (Mbps) (1) |
2.048 |
34.368 |
1.544 |
44.736 |
51.84 |
155.52 |
622.08 |
2,488 |
Note:
(1) Maximum bandwidth is equal to or greater than the data rate.
E1 and E3 are the European standards for digital transmission; T1 and T3 are the corresponding North American standards for digital transmissions. SONET/SDH standards provide data transmission over fiber optics. Cyclone devices can be used to implement the framers of all these protocols and connect to the transceiver devices.
Cyclone devices can also be used to implement the POS-PHY and UTOPIA communications interface protocols shown in Table 3.
| Table 3. Communications Interface Protocol Support in Cyclone Devices |
| Protocol |
POS-PHY Level 2 |
POS-PHY Level 3 |
UTOPIA Level 2 |
UTOPIA Level 3 |
| Maximum Bandwidth (Mbps) (1) |
622 |
2,488 |
622 |
2,488 |
| Bus Width |
16 |
8/32 |
8/16 |
8/16/32 |
Note:
(1) Maximum bandwidth is greater than the data rate.
POS-PHY and UTOPIA protocols provide physical and link layer interfaces for SONET/SDH and asynchronous transfer mode (ATM) respectively. They can be implemented in Cyclone devices.
These communications and interface protocols are used in low-end and mid-range communications equipment. Cyclone devices provide the performance, logic density, and system features required to support these applications.
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