Altera's MAX® II family of CPLDs are the lowest power, lowest cost CPLDs ever. MAX II CPLDs are based on a groundbreaking architecture that delivers the lowest power and the lowest cost per I/O pin of any CPLD family. With the introduction of the MAX IIZ CPLDs, there are now three variants that all use the same innovative CPLD architecture:
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MAX II CPLD
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MAX IIG CPLD
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MAX IIZ CPLD
This instant-on, non-volatile CPLD family targets general-purpose, low-density logic and portable applications, such as cellular handset design. In addition to delivering the lowest cost for traditional CPLD designs, MAX II CPLDs drive power and cost improvements to higher densities, enabling you to use MAX II CPLDs in place of higher power or higher cost ASSPs and standard-logic CPLDs.
Advanced features
MAX II CPLDs enable a high level of functional integration to reduce system design costs. This section describes the advanced features found in MAX II CPLDs.
- One-tenth the power consumption (compared to previous-generation 3.3-V MAX CPLDs)
- 1.8-V core voltage for reduced power consumption and increased reliability
- CPLD industry's lowest standby specification, allowing longer use in battery powered applications
- Auto start/stop capability for turning off the CPLD when not in use
- Four times the density at half the price (compared to previous-generation MAX CPLDs)
- Designed for minimum die size, giving the lowest cost per I/O pin in the industry
- Support for internal clock frequency rates of up to 300 MHz
- Twice the performance (compared to 3.3-V MAX CPLDs)
- On-board oscillator and user flash memory
- Reduces chip count by eliminating discrete oscillators or non-volatile storage devices
Real-time in-system programmability (ISP)
- Capable of downloading a second design while the device is operational
- Reduces the cost of remote field updates
- On-chip voltage regulator accepts 3.3-V, 2.5-V, or 1.8-V supply
- Simplifies board design with fewer power rails
Parallel flash loader megafunction
- Improves configuration efficiency of non-JTAG-compliant flash devices on the board
- Simplifies board management by allowing JTAG command implementation via the MAX II CPLD
- MultiVolt I/O capability allows interface with devices at 1.5-V, 1.8-V, 2.5-V, or 3.3-V logic levels
- Schmitt triggers, programmable slew rate, and programmable drive strength improve signal integrity
- Altera’s no-cost Quartus® II Web Edition software supports all MAX II CPLDs and optimizes pin-locked fitting and performance
- New MAX+PLUS® II look-and-feel option in the Quartus II software enhances ease of use
Applications
MAX II CPLDs target common control path applications, including:
- Power-up sequencing
- System configuration
- I/O expansion
- Interface bridging
