This page describes the different memory spaces and interfaces for Excalibur devices:
Table 1 contains the memory configurations for Excalibur devices.
Notes:
1. SDR = Single data rate
2. DDR = Double data rate
SRAM
To maximize the performance of the ARM922T processor, Excalibur devices contain SRAM that is usable as internal code space, data memory, or both, depending on the application. SRAM runs at up to 200 MHz and is accessible by both AHB1 and AHB2; the memory runs from the AHB1 clock. The SRAM's dual block architecture allows AHB1 and AHB2 to each concurrently access one exclusive, independently arbitrated block.
For more information about the Excalibur devices' on-chip SRAM, refer to the Excalibur Devices Overview data sheet and the Excalibur Devices Hardware Reference Manual.
Dual-Port SRAM
In addition to the SRAM, one or two blocks of dual-port SRAM can reside on each Excalibur device and are accessible from the stripe (via AHB1 and AHB2) and the FPGA. Dual-port SRAM can also serve as the application interface for sharing data between the processor and the FPGA. Alternatively, both sides of the dual-port SRAM are accessible by the FPGA. In devices with more than one block of dual-port SRAM, the memory may be multiplexed to increase either the width or depth of the available dual-port memory.
For more information about Excalibur devices' on-chip dual-port SRAM, refer to the Excalibur Devices Overview data sheet and the Excalibur Devices Hardware Reference Manual.
The SDRAM controller in the processor can support two blocks of up to 256 Kbytes each (or a total of 512 Kbytes) of SDRAM. Up to four banks per block of SDRAM can be supported for optimized performance. The SDRAM controller supports 16- or 32-bit-wide memories, depending on device (for full details, see Table 1). Single-beat, fixed-length incremental, fixed-length wrapping, and undefined-length incremental transfers are implemented; eight-beat fixed length bursts are used for data transfers and early termination is accepted.
The SDRAM controller supports both SDR and DDR SDRAM memories of up to 133 MHz and 266 MHz, respectively. The SDRAM controller runs asynchronously to both AHB1 and AHB2, timed by its own phase-locked loop (PLL).
For more information about the Excalibur devices' SDRAM controller, refer to the Excalibur Devices Overview data sheet and the Excalibur Devices Hardware Reference Manual.
Expansion Bus Interface
The expansion bus interface (EBI) is a 16-bit-wide, bidirectional external memory interface, and acts as a bridge between AHB2 and external SRAM, flash, or memory mapped devices. The EBI controller runs synchronously to the AHB2 clock and supports all valid advanced high-performance bus (AHB) transaction types, including split transactions (which allows for rate adapting between slow, external memory or memory-mapped peripherals without causing a bottleneck on the AHB2 bus).
The EBI contains four blocks of up to 32 Mbytes of external memory or memory-mapped peripherals, each configurable as 8- or 16-bits wide. This interface attaches the flash memory used in boot-from-flash mode, in which EBI block 0 (EBI0) is mapped to address zero at power-up or reset. Moreover, the EBI is an AHB2 slave and may be either synchronous or asynchronous to AHB2.
For more information about the Excalibur devices EBI, refer to the Excalibur Devices Overview data sheet and the Excalibur Devices Hardware Reference Manual.
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