APEX II Questions & Answers
On this page you can find answers to your questions about the APEX II device family. Questions are categorized under the following topics:
Q. What is the APEX II device family?
A. The APEX II device family is the next-generation APEX system-on-a-programmable-chip (SOPC) solution from Altera. APEX II FPGAs include new and enhanced features that provide unmatched flexibility and performance, enabling cutting-edge SOPC applications. Building on the successful APEX architecture, the APEX II device family marks a breakthrough in capability and system performance that will, for the first time, place programmable logic directly in the data path of high-performance communication applications.
Q. Where can I use APEX II devices?
A. By coupling huge advancements made in I/O performance and flexibility with a fast, high-density core, APEX II devices can now sit directly in the data path-offering the short time-to-market and customization benefits typically associated with PLDs.
Historically, PLDs have been restricted to control signal paths of performance-intensive, high-bandwidth applications. The inability to receive, process, and transmit large amounts of high-speed data prevented PLDs from implementing functions that involved direct interaction and processing of high-speed data.
The high-speed APEX II device core and its I/O features place this device at the center of high-performance networking and communications technologies to combine multiple functions onto a single chip, partition complex functions into multiple chips, and complement ASSPs.
Q. Why is the naming convention for APEX II devices different than other Altera FPGA families?
A. The APEX II nomenclature is based on logic elements (LEs) rather than system gates. As PLDs become more and more complex, it becomes increasingly difficult to represent logic density, features, and memory using a single unit of measure. An LE-based nomenclature more accurately communicates the logic capacity of programmable logic devices, instead of using gate counts that do not follow a defined, PLD industry standard. Disproportionate growth in embedded memory and logic elements leads to unbalanced weighting in gate enumeration and ultimately to misleading density representations. An LE-based nomenclature will facilitate better device selection and avoid confusion that could result from using a gate-based nomenclature.
Q. What densities will be available and in what packages?
A. The APEX II family consists of four family members as outlined in the Table 1:
| Table 1: APEX II Device Overview |
| Device |
EP2A15
|
EP2A25
|
EP2A40
|
EP2A70
|
| Typical gates |
600,000
|
900,000
|
1,500,000
|
3,000,000
|
| Logic elements |
16,640
|
24,320
|
38,400
|
67,200
|
| Embedded system blocks (ESBs) |
104
|
152
|
160
|
280
|
| Maximum RAM bits |
425,984
|
622,592
|
655,360
|
1,146,880
|
| True-LVDSTM channels |
36 Input
36 Output
|
36 Input
36 Output
|
36 Input
36 Output
|
36 Input
36 Output
|
Flexible-LVDSTM channels
|
56 Input
56 Output
|
56 Input
56 Output
|
88 Input
88 Output
|
88 Input
88 Output
|
| Maximum user I/Os |
492
|
607
|
735
|
1,060
|
| Package Options |
724-Pin BGA
672-Pin FBGA
|
724-Pin BGA
672-Pin FBGA
1,020-Pin FBGA
|
724-Pin BGA
672-Pin FBGA
1,020-Pin FBGA
|
724-Pin BGA
1,508-Pin FBGA
|
Q. What speed grades will be available?
A. APEX II devices will be available in -7, -8, and -9 speed grades, with -7 being the fastest.
Q. Are APEX II devices backward-compatible with APEX 20K, APEX 20KE, and APEX 20KC devices?
A. APEX II devices are not drop-in compatible with APEX 20K, APEX 20KE, and APEX 20KC devices. Although largely based upon the APEX 20K architecture, many enhancements were made to achieve the high levels of I/O performance in APEX II devices, and compatibility could not be supported. However, APEX 20K designs can be easily resynthesized for APEX II devices in the Quartus II and third-party software.
Q. What are the key differences between APEX II devices and APEX 20K, APEX 20KE, and APEX 20KC devices?
A. APEX II devices build on the APEX 20KE architecture. Excellent low-voltage differential signaling (LVDS) performance, larger densities, and brand-new I/O capabilities highlight the significant differences between the families. Additionally, APEX II devices have double the amount of memory and phase-locked loops (PLLs) compared to equivalent APEX 20KE devices.
Q. What process technology will be used in APEX II devices?
A. APEX II devices will be manufactured on a 1.5-V, 0.15-µm, 8-layer-metal, all-copper process technology.
Q. Why do all layers use copper?
A. An all-layer copper interconnect offers significant flexibility in balancing metal pitch and thickness. Copper interconnects present lower electrical resistance, thus improving performance by reducing interconnect delays seen in many integrated circuits. The low resistance in copper makes it one of the best-known conductors of electricity, dramatically reducing interconnect delays. This results in a performance-optimized process that is much more efficient than aluminum-copper hybrid process technologies. Furthermore, future advanced process technologies that utilize finer transistors must be manufactured on an all-layer-copper process.
Q. How much embedded memory is available?
A. Each embedded system block (ESB) accommodates up to 4-Kbits of memory, capable of implementing first-in, first-out (FIFO) functions, RAM, and content-addressable memory (CAM). With up to 280 ESBs per device, designers have over 1.1 Mbits of RAM available for storing anything from incoming high-speed data to instruction codes for soft processor cores. Each ESB can be partitioned into equivalent 2K blocks, effectively doubling the number of ESBs in the device, or they can be seamlessly stitched together to form larger, aggregate structures-all without degradation in performance.
Q. How many PLLs are available?
A. APEX II devices have up to eight on-board PLLs. Four general-purpose PLLs are available for clock synthesis, each featuring two taps that directly drive an individual global clock net. These four general-purpose PLLs also can drive two external pins for external system clock management. Up to four True-LVDS PLLs are on each APEX II device. A pair of PLLs drives the LVDS receiver clock domains and the other pair drives the LVDS transmit clock domains. The LVDS transmit PLLs feature individual off-chip outputs.
Q. Are there any dedicated multipliers?
A. APEX II devices do not have dedicated multipliers. However, they do support lpm_mult, a megafunction available in the Quartus II software. This implements multiplication operations in logic elements, achieving superior, pipelined performance to implementations using non-registered, dedicated circuitry.
Q. Can APEX II devices interface with high-speed external memory devices?
A. For memory-intensive functions that require more RAM than the provided ESBs, APEX II devices can communicate with the latest SRAM and SDRAM technologies. 200-MHz ZBT, 334-Mbps DDR, and 668-Mbps QDR SRAMs are all supported interfaces, as well as 334-Mbps DDR SDRAMs. This capability is possible due to the dedicated circuitry and the six registers in each I/O element.
Q. How is LVDS supported in APEX II devices?
A. APEX II devices feature both the True-LVDS solution at up to 1-Gbps and the Flexible-LVDS solution at up to 624-Mbps. With over 182-Gbps differential bandwidth, the APEX II LVDS solution provides unparalleled performance and flexibility for high-bandwidth data path applications.
1-Gbps True-LVDS circuitry: APEX II devices incorporate dedicated, high-speed circuitry for achieving 1-Gbps LVDS performance. This includes dedicated serialization/deserialization circuitry, high-performance phase-locked loops (PLLs), Clock-Data Synchronization (CDS) circuitry and true differential I/O buffers. Each LVDS channel features equivalent LVPECL, HyperTransport, and PCML performance.
624-Mbps Flexible-LVDS circuitry: Using dedicated differential I/O buffers, APEX II devices can achieve 624-Mbps LVDS performance. Equivalent performance is supported for LVPECL and HyperTransport.
Q. How many LVDS channels are available in APEX II?
A. All densities include 36 input and 36 output True-LVDS channels. These channels are subdivided into four banks that have independent clock domains, capable of operating at different frequencies. The EP2A15 and EP2A25 devices have 56 input and 56 output Flexible-LVDS channels and the EP2A40 and EP2A70 devices feature 88 input and 88 output channels. These channels result in a total differential bandwidth of up to 182 Gbps.
Q. What is CDS circuitry?
A. Clock-data synchronization (CDS) circuitry individually synchronizes each True-LVDS channel with a single system clock. Unlimited amounts of fixed, channel-to-channel or clock-to-channel skew can be resolved, allowing a single APEX II device to be driven by up to 36 individual, high-speed sources. CDS reduces printed circuit board design complexity by eliminating the need to miter traces, helping to balance the delays incurred between the high-speed sources and the receiving APEX II device. These delays can be attributed to internal device characteristics such as varying output timing characteristics and external factors such as varying trace lengths.
Q. When will the first engineering samples be available?
A. The EP2A15 device in the 672-pin FineLine BGATM package is available now. The EP2A25 device will be available soon.
Q. How much will APEX II devices cost?
A. Volume pricing for mid-2002 will begin at $130 for the EP2A15 device.
Q. What single-ended I/O standards are supported in APEX II devices?
A. APEX II devices feature new and enhanced single-ended I/O standard support, which includes 250-MHz HSTL Class I & II, 167-MHz SSTL 2/3 Class I & II, GTL+, AGP, and CTT.
Q. What physical layer bus transfer protocols are supported?
A. APEX II devices include extensive support for the most popular physical layer bus transfer protocols:
Host Processor Interfaces: RapidIO, HyperTransport, PCI-X
PHY-Link Layer Interfaces: POS-PHY Level 4, Utopia IV, Flexbus
Switch Fabric Interfaces: CSIX, LCS
Q. Will APEX II devices be supported in the Quartus II software?
A. APEX II devices will be supported in the Quartus II software version 1.1. The Quartus II software delivers superior designer productivity and supports system-level designs with features including the PowerFit fitter technology, advanced floorplanning capabilities, support for multi-million-gate devices, and seamless integration with third-party tools. Industry-leading compile times minimize design iteration times, while unleashing the full potential of APEX II devices.
Q. What IP cores will be available for APEX II devices?
A. Intellectual property (IP) core support in APEX II devices will be extensive- ranging from external memory device interfacing such as zero bus turnaround synchronous random access memory (ZBT SRAM) controllers to advanced high-speed physical layer standards such as RapidIO and POS-PHY Level 4. Additionally, all existing MegaCoreTM or AMPPSM megafunctions will be fully supported in APEX II devices.
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