Literature Licensing Buy On-Line Download Entire Site Part Number Knowledge DB

Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line

Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature

FPGAs       Stratix IV (E and GX)       Stratix III       Stratix II       Stratix       Stratix GX       Stratix II GX       Arria GX       Cyclone III       Cyclone II       Cyclone     CPLDs       MAX II       MAX 3000A       MAX 7000     ASICs       HardCopy III       HardCopy II       HardCopy     By End Market       Automotive       Broadcast       Consumer       Medical     Configuration       Configuration Devices     Mature Products       Product Listing     Design Software       Quartus II       System-Level Software       MAX+PLUS II     IP/Embedded Processors    IP Megafunctions           Embedded Processors           Interfaces & Peripherals           DSP           Communications       Nios II Processor       Nios Processor       SOPC Builder     By Technology    Technologies     By Type       Application Briefs       Application Notes       Conference Papers       Data Sheets       Device Pin-Outs       Errata Sheets       Functional Specifications       Manuals       Release Notes       Technical Briefs       User Guides       White Papers     General Documentation       Annual Reports       Brochures       Customer Notifications       Design Contest Papers       Glossary of Altera Terms       Inserts and Advertorials       Reliability Report       SEC Filings       Selector Guides       Sparkle Sheets     Email/E-Newsletter Sign Up       Subscribe Now       Manage Your Subscriptions       View E-Newsletter Archives       News & Views Ezine     Literature Update Sign Up       Subscribe Now       Manage Your Subscriptions       View Recent Updates       FAQ     RSS/XML News Feeds       Subscribe Now

Home > Products > Literature > IP Megafunctions > Embedded Processors Print This Page Subscribe to Email Literature: IP Embedded Processors Intellectual Property (IP): Embedded Processors Title Doc Version Release Date File Size Document Part Number Data Sheets Nios 3.0 CPU Data Sheet 2.2 Nov 2004 283 KB DS-NIOSCPU-2.2 Active Serial Memory Interface Data Sheet 1.2 Jun 2003 99 KB DS-NIOSSRLMRY-1.2 Legacy SDRAM Controller with Avalon Interface Data Sheet 1.0 Jan 2003 176 KB DS-NSSTXSRDM-1.0L Nios DMA Data Sheet 1.2 Jul 2003 350 KB DS-NIOSDMA-1.2 Nios PIO Data Sheet 3.1 Jan 2003 303 KB DS-NIOSPIO-3.1 Nios SPI Data Sheet 2.1 Jan 2003 324 KB DS-NIOSSPI-2.1 Nios Timer Data Sheet 3.2 Jul 2003 239 KB DS-NIOSTIM-3.2 Nios UART Data Sheet 3.0 Jan 2003 409 KB DS-NIOSUART-3.0 SDRAM Controller with Avalon Interface Data Sheet 2.0 Jul 2003 252 KB DS-NSSTXSDRM-2.0 Application Notes AN 320: OpenCore Plus Evaluation of Megafunctions 1.6 Nov 2007 307 KB AN-320-1.6 AN 299: System Development Tools for Excalibur Devices 1.1 Jun 2003 618 KB AN-299-1.1 AN 298: Reconfiguring Excalibur Devices Under Processor Control      AN 298: Design Files (1 MB) 1.0 Feb 2003 705 KB AN-298-1.0 AN 287: Using Excalibur DMA Controllers for Video Imaging      AN 287: Design Files (7 MB) 1.1 Feb 2003 664 KB AN-287-1.1 AN 284: Implementing Interrupt Service Routines in Nios Systems      Example Code (5 KB) 1.0 Jan 2003 335 KB AN-284-1.0 AN 278: Excalibur Dynamic Reconfiguration with Linux Demonstration      AN 278: Design Files (17 MB) 2.0 Jun 2003 811 KB AN-278-2.0 AN 244: Using Run-From-Flash Mode with the Excalibur Bootloader 1.0 Sep 2002 140 KB AN-244-1.0 AN 242: Excalibur Solutions - Simple Excalibur System      AN 242: Design Files (468 KB) 1.0 Aug 2002 245 KB AN-242-1.0 AN 240: Simulating Excalibur Systems 1.0 Sep 2002 335 KB AN-240-1.0 AN 196: Excalibur Software Debugging Solutions 1.2 Aug 2002 147 KB AN-196-1.2 AN 192: Excalibur Solutions - Embedded Stripe Performance Designs      AN 192: Design Files (346 KB) 1.2 Nov 2002 253 KB AN-192-1.2 AN 191: Excalibur Solutions - Using the Interrupt Controller      AN 191: Design Files (370 KB) 1.3 Dec 2002 202 KB AN-191-1.3 AN 189: Simulating Nios Embedded Processor Designs 2.1 Feb 2003 1 MB AN-189-2.1 AN 188: Custom Instructions for the Nios Embedded Processor 1.2 Sep 2002 313 KB AN-188-1.2 AN 187: Booting Excalibur Devices      AN 187: Design Files (574 KB) 1.2 Mar 2003 632 KB AN-187-1.2 AN 184: Simultaneous Multi-Mastering with the Avalon Bus 1.1 Apr 2002 135 KB AN-184-1.1 AN 181: Excalibur Solutions - Multi-Master Reference Design      AN 181: Design Files (804 KB) 2.3 Nov 2002 642 KB AN-181-2.3 AN 178: Estimating Nios Resource Usage & Performance 1.0 Sep 2001 224 KB A-AN-178-1.0 AN 177: Excalibur Solutions-Using the Excalibur Stripe PLLs 1.3 Jul 2002 300 KB A-AN-177-1.3 AN 173: Excalibur Solutions - DPRAM Reference Design      AN 173: Design Files (326 KB) 2.3 Aug 2002 208 KB A-AN-173-2.3 AN 143: Excalibur Solutions - Using the Expansion bus Interface 1.0 Oct 2002 991 KB A-AN143-1.0 AN 142: Excalibur Solutions - Using the Embedded Stripe Bridges 2.1 Jun 2002 432 KB A-AN142-2.1 AN 141: Excalibur Solutions - Using the SDRAM Controller 1.0 Sep 2002 926 KB A-AN141-1.0 Manuals EPXA1 Development Board Hardware Reference Manual 1.1 Sep 2002 3 MB MNL-EPXA1DEVBD-1.1 EPXA10 DDR Development Board Hardware Reference Manual 1.3 Apr 2003 3 MB MNL-EXCDDRDEVBRD-1.3 EPXA10 Development Board Hardware Reference Manual 1.1 Apr 2002 1 MB MNL-EPXA10DEVBD-1.1 Nios Development Board Cyclone II Edition Reference Manual (RoHS Compliant)      Nios Development Board Cyclone II PCB Layout Files (35 MB)      Nios Development Board Cyclone II 2C35 Schematic (762 KB) 1.3 May 2007 1 MB MNL-N051805-1.3 Nios Development Board Stratix II Edition Reference Manual (RoHS Compliant)      Nios Development Board Stratix II Edition PCB Layout Files (5 MB)      Nios Development Board Stratix II Edition Schematic (789 KB) 1.3 May 2007 1 MB MNL-01001-1.3 Nios Embedded Processor 32-Bit Programmer's Reference Manual 3.1 Jan 2003 4 MB MNL-NIOS32PROG-3.1 Nios Embedded Processor Software Development Reference Manual 3.2 Mar 2003 1 MB MNL-NIOSPROG-3.2 Plugs Ethernet Library Reference Manual 1.2 Jul 2003 880 KB MNL-SOPCTHRNT-1.2 User Guides EPXA1 Development Kit Getting Started User Guide      EPXA1 Development Kit Design Files (81 KB) 1.3 Jan 2003 449 KB UG-EPXA1-1.3 EPXA10 DDR Development Kit Getting Started User Guide      EPXA10 DDR Development Kit Design Files (76 KB) 1.4 Feb 2003 830 KB UG-EPXA10DDR-1.4 EPXA10 Development Kit Getting Started User Guide      EPXA10 Development Kit Design Files (76 KB) 3.2 Nov 2002 476 KB UG-EPXA10-3.2 Excalibur Bus Functional Model User Guide 1.2 Jul 2002 520 KB A-UG-XBUS-1.2 Excalibur Hardware Design Tutorial 1.5 Aug 2002 524 KB A-MNL_ARMTUTORIAL-1.5 Excalibur Stripe Simulator User Guide 1.5 Mar 2003 1 MB UG-EXCFSSIM-1.5 Nios II Embedded Evaluation Kit Cyclone III Edition User Guide      Nios II Embedded Evaluation Kit Cyclone III Edition BOM (238 KB)      Nios II Embedded Evaluation Kit Cyclone III Edition Layout (2 MB)      Nios II Embedded Evaluation Kit Cyclone III Edition Quick Start Guide (1 MB)      Nios II Embedded Evaluation Kit Cyclone III Edition Reference Manuals (2 MB)      Nios II Embedded Evaluation Kit Cyclone III Edition Schematic (1 MB) 1.0 Jan 2008 1 MB UG-01025 Tutorials Nios Custom Instructions Tutorial 1.0 Jun 2002 645 KB TU-NIOSCITTRL-1.0 Nios Software Development Tutorial      Design Files for the Tutorial (1 MB) 1.3 Jul 2003 912 KB TU-NIOSSFTWR-1.3 Using SOPC Builder with Excalibur Devices Tutorial      Design Files for the Tutorial (11 KB) 1.1 Jun 2003 954 KB TU-SOPCTTRL1.1 Third-Party Literature ARM Architecture Reference Manual 1.0 Nov 2000 13 MB ARM DDI 0100E ARM9TDMI Technical Reference Manual rev 3 Nov 2000 920 KB ARM DDI 0180A Embedded Trace Macrocell (ETM9) Technical Reference Manual 2A Jun 2001 1 MB ARM DDI 0157E GNUPro Toolkit User´s Guide for ARM and ARM / Thumb Development   Feb 1900 735 KB   Errata Sheets MegaCore IP Library Release Notes and Errata (All IP and Nios II errata and release notes are combined into one document beginning with version 7.2) 8.0.1 Jul 2008 1 MB RN-IP-2.1 PDF Legal Notice Rate This Page

Please Give Us Feedback

Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On-Line  Devices | Design Software | Intellectual Property | Design Services | Dev. Kits/Cables | Literature  Contact Us | Site Help | Site Map | Privacy | Legal Notice  Copyright © 1995-2008 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation