Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 FPGAs
      Stratix IV (E and GX)
      Stratix III
      Stratix II
      Stratix
      Stratix GX
      Stratix II GX
      Arria GX
      Cyclone III
      Cyclone II
      Cyclone
  
 CPLDs
      MAX II
      MAX 3000A
      MAX 7000
  
 ASICs
      HardCopy III
      HardCopy II
      HardCopy
  
 By End Market
      Automotive
      Broadcast
      Consumer
      Medical
  
 Configuration
      Configuration Devices
  
 Mature Products
      Product Listing
  
 Design Software
      Quartus II
      System-Level Software
      MAX+PLUS II
  
 IP/Embedded Processors
   IP Megafunctions
      Nios II Processor
      Nios Processor
      SOPC Builder
  
 By Technology
   Technologies
  
 By Type
      Application Briefs
      Application Notes
      Conference Papers
      Data Sheets
      Device Pin-Outs
      Errata Sheets
      Functional Specifications
      Manuals
      Release Notes
      Technical Briefs
      User Guides
      White Papers
  
 General Documentation
      Annual Reports
      Brochures
      Customer Notifications
      Design Contest Papers
      Glossary of Altera Terms
      Inserts and Advertorials
      Reliability Report
      SEC Filings
      Selector Guides
      Sparkle Sheets
  
 Email/E-Newsletter Sign Up
      Subscribe Now
      Manage Your Subscriptions
      View E-Newsletter Archives
      News & Views Ezine
  
 Literature Update Sign Up
      Subscribe Now
      Manage Your Subscriptions
      View Recent Updates
      FAQ
  
 RSS/XML News Feeds
      Subscribe Now
  

Literature: White Papers

Download the latest version of Adobe Acrobat Reader
Title Doc Version Release Date File Size Document Part Number
White Papers
40-nm FPGAs and the Defense Electronic Design Organization New 1.0Jul 2008313 KBWP-01064-1.0
Anti-Tamper Capabilities in FPGA Designs New 1.0Jul 2008310 KBWP-01066-1.0
DO-254 Support for FPGA Design Flows New 1.0Jul 200891 KBWP-01065-1.0
Military Benefits of the Managed Risk Process at 40 nm New 1.0Jul 2008993 KBWP-01063-1.0
Military Productivity Factors in Large FPGA Designs New 1.0Jul 2008443 KBWP-01067-1.0
DPA Circuitry and rx_dpa_locked Signal Behavior in Stratix III Devices New 1.0Jun 2008204 KBWP-01068-1.0
Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers1.0May 20083 MBWP-01057-1.0
Increasing Productivity With Quartus II Incremental Compilation1.0May 2008169 KBWP-01062-1.0
Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices1.0May 2008371 KBWP-01058-1.0
Stratix IV FPGA Power Management and Advantages1.0May 20082 MBWP-01059-1.0
Supporting Unknown FREF Video Applications With PLLs
     Unknown FREF Reference Design (931 KB)
1.0Mar 2008172 KBWP-01056-1.0
FPGA Run-Time Reconfiguration: Two Approaches1.0Mar 2008362 KBWP-01055-1.0
Increase Performance in Imaging Applications by Integrating DSP Functions With FPGAs1.2Mar 200853 KBWP-AAB090505-1.2
Increase Performance in Video and Image Processing Applications With FPGA Integration1.2Mar 200858 KBWP-AAB090705-1.2
Low-Cost Integration of Serial EEPROMs and Flash Memory Devices1.2Mar 200884 KBWP-LWCST05-1.2
Reduce Manufacturing Costs by Integrating Flash Device Programming1.2Mar 200846 KBWP-92005-1.2
Reduce System Costs By Integrating PCI Interface Functions Into CPLDs1.3Mar 2008116 KBWP-AAB090305-1.3
Using FPGA-Based Channel Bonding for HDTV Over DSL1.0Feb 2008152 KBWP-01053-1.0
Enabling New Infotainment-Equipment Cost Structures With Open-System Architectures1.0Feb 2008757 KBWP-01054-1.0
The Quest for Digital Broadcast Quality: Addressing Quality Hot Spots1.2Feb 2008679 KBWP-01022-1.2
Comparing IP Integration Approaches for FPGA Implementation1.1Feb 2008195 KBWP-01032-1.1
Reducing the Cost of Wireless Backhauling Through Circuit Emulation1.0Jan 20082 MBWP-01049-1.0
Developing MSAN Equipment Using Low-Cost FPGAs1.1Jan 2008624 KBWP-01046-1.1
Electronic Warfare Design With PLDs and High-Speed Transceivers1.0Dec 20071 MBWP-01052-1.0
Reduce Total System Cost in Portable Applications Using MAX II CPLDs2.1Dec 2007504 KBWP-01001-2.1
Using Zero-Power CPLDs to Substantially Lower Power Consumption in Portable Applications1.1Dec 2007676 KBWP-01042-1.1
Basic Principles of Signal Integrity1.3Dec 2007548 KBWP-SGNLNTGRY-1.3
Six Ways to Replace a Microcontroller With a CPLD1.1Dec 2007800 KBWP-01041-1.1
Guidance for Accurately Benchmarking FPGAs1.2Dec 2007848 KBWP-01040-1.2
Custom NPUs for Broadband Access Line Cards1.0Dec 2007639 KBWP-01048-1.0
Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace1.0Nov 20071 MBWP-01047-1.0
Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces1.0Nov 2007812 KBWP-01034-1.0
Floating-Point Compiler: Increasing Performance With Fewer Resources1.0Nov 2007542 KBWP-01050-1.0
FPGA Power Management and Modeling Techniques1.0Nov 2007696 KBWP-01044-1.0
Addressing SWaP Challenges in Military Platforms With 65-nm FPGAs and Structured ASICs1.0Oct 2007792 KBWP-01045-1.0
DSP-FPGA System Partitioning for MIMO-OFDMA Wireless Basestations1.0Oct 2007972 KBWP-01043-1.0
A Flexible Solution for Industrial Ethernet1.0Oct 2007699 KBWP-01037-1.0
Gain Flexibility and Increased Integration With Advanced Cyclone III FPGA PLLs1.0Oct 20071 MBWP-01036-1.0
Accelerating High-Performance Computing With FPGAs1.1Oct 2007956 KBWP-01029-1.1
An FPGA Design Security Solution Using a Secure Memory Device1.0Oct 2007510 KBWP-01033-1.0
Designing High-Performance DSP Hardware Using Catapult C Synthesis and the Altera Accelerated Libraries1.0Oct 2007687 KBWP-01039-1.0
Performing Equivalent Timing Analysis Between Altera Classic Timing Analyzer and Xilinx Trace3.0Oct 20071 MBWP-TMANAL-3.0
Stratix III FPGAs vs. Xilinx Virtex-5 Devices: Architecture and Performance Comparison2.1Oct 2007949 KBWP-01007-2.1
Optimizing Radar and Advanced Sensors Functions With FPGAs1.0Sep 20071,007 KBWP-01038-1.0
Driving Flexibility Into Automotive Electronics Design1.1Sep 2007239 KBWP-01025-1.1
Implementation of the Smith-Waterman Algorithm on a Reconfigurable Supercomputing Platform1.0Sep 20071 MBWP-01035-1.0
FPGA Performance Benchmarking Methodology1.6Aug 2007246 KBWP-FPGAPBM-1.6
Customizing Multi-Service Access Network Silicon1.0Aug 2007724 KBWP-01030-1.0
Designing and Using FPGAs for Double-Precision Floating-Point Math1.1Aug 2007683 KBWP-01028-1.1
Designing Home Appliances With FPGAs1.0Jul 2007617 KBWP-01027-1.0
Architecture and Component Selection for SDR Applications1.0Jun 2007615 KBWP-01026-1.0
Quality of Service in Home Networking1.0May 2007640 KBWP-01024-1.0
FPGA vs. DSP Design Reliability and Maintenance1.1May 2007147 KBwp-01023-1.1
Stratix III Programmable Power1.1May 2007632 KBWP-01006-1.1
Achieving Low Power in 65-nm Cyclone III FPGAs1.1Apr 2007699 KBWP-01016-1.1
Designing With Confidence for Military SDR Production Applications1.1Apr 20072 MBWP-01020-1.1
A Flexible Architecture to Drive Sharp Two-Way Viewing Angle and Standard LCDs1.2Mar 20072 MBWP-01014-1.2
Broadcast Video Infrastructure Implementation Using FPGAs1.2Mar 2007596 KBWP-BRDCST0306-1.2
Satisfying the Demand for Rapid Feature Enhancement in Consumer Display Products1.0Mar 2007980 KBWP-01015-1.0
Using Cyclone III FPGAs for Clearer LCD HDTV Implementation1.0Mar 2007214 KBWP-01018-1.0
Using Cyclone III FPGAs for Emerging Wireless Applications1.0Mar 2007683 KBWP-01017-1.0
Video and Image Processing Design Using FPGAs1.1Mar 2007488 KBWP-VIDEO0306-1.1
Video Surveillance Implementation Using FPGAs1.1Mar 2007507 KBWP-VIDEOSRVL-1.1
SEmulation: Turbocharging the FPGA Development Process1.0Mar 20071 MBWP-01021-1.0
Robust SEU Mitigation With Stratix III FPGAs1.0Feb 2007801 KBWP-01012-1.0
Design Security in Stratix III Devices1.4Nov 2006288 KBWP-01010-1.4
Stratix III FPGA Signal Integrity1.0Nov 2006797 KBWP-01008-1.0
Altera's Strategy for Delivering the Benefits of the 65-nm Semiconductor Process1.1Sep 2006345 KBWP-01002-1.1
Stratix II Performance and Logic Efficiency Analysis2.0Sep 20061 MBWP-STXIIPLE-2.0
Stratix II vs. Virtex-4 Performance Comparison2.0Sep 2006505 KBWP-S2052505-2.0
FPGA Architecture1.0Sep 2006637 KBWP-01003-1.0
Building Flexible, Cost-Efficient Broadband Access Equipment Line Cards1.0Sep 2006303 KBWP-01005-1.0
Programmable Platform Solutions1.0Aug 2006756 KBWP-01004-1.0
Reduce Total System Cost in Portable Applications Using MAX II CPLDs1.0Jul 2006445 KBWP-01001-1.0
Stratix II DDR2 System Validation Summary1.0May 20061 MBWP-S2DDR2SVS-1.0
Automated Generation of Hardware Accelerators With Direct Memory Access From ANSI/ISO Standard C Functions1.0May 2006296 KBWP-AGHRDWR
TimeQuest Timing Analyzer: Native SDC Support for Timing Analysis of FPGA-Based Designs1.0May 2006792 KBWP-TMQST-1.0
Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices1.1May 2006319 KBWP-HTSCKTNG-1.1
Medical Imaging Implementation Using FPGAs1.0Apr 2006190 KBWP-MEDICAL-1.0
IPTV’s Key Broadcast Building Blocks1.0Apr 2006486 KBWP-BRDCST-1.0
3-Gbps SDI Video (SMPTE 424M)1.0Apr 2006332 KBWP-3GBPS-1.0
MAX II I/O Characteristics During Hot Socketing1.0Mar 2006463 KBWP-M2HTSCKNG-1.0
Traffic Management for Testing Triple-Play Services1.0Mar 2006461 KBWP-TRFFC-1.0
Low-Cost FPGA Solution for PCI Express Implementation1.0Mar 2006148 KBWP-LWCST-1.0
FPGA Integration Increases Flexibility, Reduces Cost in Consumer Applications1.1Feb 2006204 KBWP-AAB090205-1.1
Gain Flexibility, Lower Costs in Display Control Through Integration With FPGAs1.1Feb 2006265 KBWP-AAB090905-1.1
Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors2.1Feb 2006494 KBWP-PLDMDCL-2.1
Increase Flexibility in Layer 2 Switches by Integrating Ethernet ASSP Functions Into FPGAs1.1Feb 2006421 KBWP-AAB091005-1.1
Lower Costs in Broadcasting Applications With Integration Using FPGAs1.1Feb 2006215 KBWP-AAB090405-1.1
Optimize System Flexibility by Integrating Custom Microprocessors Into FPGAs1.1Feb 2006237 KBWP-AAB090805-1.1
Architectural Differences Between Stratix II & Stratix Devices1.1Jan 2006324 KBWP-STXIIARDF-1.1
Versatile Digital QAM Modulator1.1Jan 2006586 KBWP-STXIIQAM-1.1
Single-Resistor RSDS Solution for Cyclone II Devices1.0Oct 2005180 KBWP-C20905
Using the Intel Flash Memory-Based EPC4, EPC8 & EPC16 Devices
     EPC Programming File Conversion Utility (108 KB)
1.1Oct 2005228 KBWP-FMB1005-1.1
Using Stratix II GX in HDTV Video Production Applications2.0Sep 2005106 KBWP-STXGXDTVS-2.0
Stratix II vs. Virtex-4 Density Comparison2.2Aug 2005264 KBWP-STXIIXLNX-2.2
Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy1.0Aug 2005356 KBWP- S20805-01
Compromises of Using a 10-Gbps Transceiver at Other Data Rates1.0Jul 2005100 KBWP-032205-1.0
MAX Series Configuration Controller using Flash Memory
     Reference Design (37 KB)
1.0Jun 2005130 KBWP-M060605-1.0
Input Signal Edge Rate Guidance1.0Jun 200563 KBWP-060205-1.0
FPGAs for High-Performance DSP Applications1.1May 2005119 KBWP-041905-1.1
Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs1.0Mar 2005557 KBWP-022805-1.0
Using Parity to Detect Memory Errors in Stratix Devices1.2Feb 200597 KBWP-STXPARITY-1.2
Stratix II DSP Performance2.0Jan 2005241 KBWP-STXIIDSP-2.0
Transient Voltage Protection for Stratix GX Devices1.0Jan 2005283 KBWP-SGX012105-1.0
DDR & DDR2 SDRAM Controller Compiler FAQ1.1Dec 200466 KBWP-IPFAQ
The Efficiency of the DDR & DDR2 SDRAM Controller Compiler1.1Dec 200449 KBWP-IPDDR
Stratix vs. Virtex-II Pro FPGA Performance Analysis1.1Nov 2004146 KBWP-STXVRTXIIPFP-1.1
Accelerating WiMAX System Design with FPGAs1.0Oct 2004544 KBWP-FPGA102204-1.0
FPGA Design Security Solution Using MAX II Devices1.0Sep 200452 KBWP-M2DSGN 1.0
Selecting the Right High-Speed Memory Technology for Your System1.0Aug 2004193 KBWP-S852004-1.0
SerialLite Protcol Overview1.1Jul 2004136 KBWP-SERIALLT-1.1
Upgrading a DDR SDRAM Controller MegaCore Function v2.1.* Design to v2.2.01.0Jun 200474 KBWP-MFDDR
Benefits of Altera's High-Speed DDR2 SDRAM Memory Interface Solution1.0May 2004273 KBWP-DDRIIFPGA-1.0
The Benefits of Altera’s High-Speed DDR SDRAM Memory Interface Solution1.1May 2004358 KBWP-DDRFPGA-1.1
Using Stratix GX Devices for SONET/SDH Backplanes1.1May 2004193 KBWP-STXSNTSDH-1.1
Improving Pin-to-Pin Timing in Stratix & Stratix GX1.0Apr 2004170 KBWP-STXTCO-1.0
Implementation of CORDIC-Based QRD-RLS Algorithm on Altera Stratix FPGA with Embedded Nios Soft Processor Technology1.0Mar 2004119 KBWP-STXQRD-01
MAX II Logic Element to Macrocell Conversion Methodology1.0Mar 200472 KBWP-MXIILGC-1.0
Challenges in Manufacturing Reliable Lead Free Components1.0Feb 2004388 KBWP-CHMFGRELLDFR-1.0
Altera Hot-Socketing & Power-Sequencing Advantages1.2Feb 200479 KBWP-HTSCKT-1.2
Implementing a Queue Manager in Traffic Management Systems1.1Feb 2004125 KBWP-QMGR-1.1
The Need for Dynamic Phase Alignment in High-Speed FPGAs1.1Feb 200471 KBWP-STXGXDPA-1.1
Selecting the Correct High Speed Transceiver Solution1.0Sep 20032 MBWP-HGSPDTRNS-1.0
Using Pre-Emphasis and Equalization with Stratix GX1.0Sep 20032 MBWP-SGXEQUAL-1.0
An Analytical Review of FPGA Logic Efficiency in Stratix, Virtex-II & Virtex-II Pro Devices1.1May 2003117 KBWP-STXVSVRTX-1.1
Configuring the MicroBlaster Fast Passive Parallel Software Driver
     Source Code (25 KB)
1.0May 200361 KBWP-MCRBLSTRPLL-1.0
MorphIO: An I/O Reconfiguration Solution for Altera Devices
     Tcl File (5 KB)
     Readme File (7 KB)
1.0May 200346 KBWP-I/ORECONFIG-1.0
Soft Multipliers For DSP Applications1.0May 2003490 KBWP-DSPSFTMULT-1.0
Traffic Management in Stratix GX Devices1.0Dec 200269 KBWP-STGXTRFFC-1.0
Stratix GX in Storage Applications1.0Nov 200280 KBWP-STXSTRAPP-1.0
Stratix GX in Switch Fabric Systems1.0Nov 2002222 KBWP-STXGXSFS-1.0
The Evolution of High Speed Transceiver Technology1.0Nov 2002438 KBWP-STGXHST-1.0
FPGAs Provide Reconfigurable DSP Solutions1.0Aug 2002216 KBWP-FPGA/DSP-1.0
Implementing the MicroBlaster Configuration on the ColdFire Development Board
     Source Code for the MicroBlaster on ColdFire Board (167 KB)
1.0Feb 2002102 KBWP-MCRBLSTR-1.0
Enhancing High-Speed Telecommunications Networks with FEC1.0Feb 2001109 KBM-WP-IPRSFEC-01
5.0-Volt Tolerance in APEX 20KE Devices1.2Aug 200088 KBA-WP-APEX5V-1.2

PDF Legal Notice

  Please Give Us Feedback