Literature: Stratix III Devices
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- Chapter 1. Stratix III Device Family Overview (ver 1.4, May 2008, 258 KB)
- Chapter 2. Logic Array Blocks & Adaptive Logic Modules in Stratix III Devices (ver 1.3, May 2008, 305 KB)
- Chapter 3. MultiTrack Interconnect in Stratix III Devices (ver 1.1, Oct 2007, 172 KB)
- Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices (ver 1.4, May 2008, 354 KB)
- Chapter 5. DSP Blocks in Stratix III Devices (ver 1.3, May 2008, 498 KB)
- Chapter 6. Clock Networks & PLLs in Stratix III Devices (ver 1.4, May 2008, 974 KB)
Related Documentation
- AN 408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines (ver 2.1, Jul 2008, 4 MB)
SII Simulation Example (3 KB)
SIII Simulation Example (3 KB)
- AN 435: Using DDR and DDR2 SDRAM with Stratix III and Stratix IV Devices (ver 2.0, Aug 2008, 2 MB)
AN 435 Design Files (3 MB)
- AN 436: Using DDR3 SDRAM with Stratix III and Stratix IV Devices (ver 3.0, Aug 2008, 2 MB)
AN 436 Design Files (3 MB)
- AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix III and Cyclone III Devices (ver 3.0, Oct 2007, 306 KB)
- AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices (ver 1.1, Jul 2008, 1 MB)
Design Example for AN 461 (2 MB)
- AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction (ver 1.2, May 2008, 888 KB)
Example Design for AN 462: top.qar (2 MB)
- AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines (ver 1.0, Jun 2008, 918 KB)
- External DDR Memory PHY Interface Megafunction User Guide (ALTMEMPHY) (ver 5.0, Jul 2008, 2 MB)
- Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces (ver 1.0, Nov 2007, 812 KB)
- Stratix_III_Advertorial (ver 1.0, Aug 2007, 98 KB)
- Accelerating High-Performance Computing With FPGAs (ver 1.1, Oct 2007, 956 KB)
- AN 437: Power Optimization in Stratix III FPGAs (ver 2.0, Aug 2007, 219 KB)
- AN 448: Stratix III Power Management Design Guide (ver 1.3, May 2007, 201 KB)
- PowerPlay Early Power Estimator User Guide For Stratix III and Stratix IV FPGAs (ver 2.0, May 2008, 1 MB)
- Stratix III and Stratix IV PowerPlay Early Power Estimator (ver 8.0 SP1.1, Aug 2008, 18 KB)
PowerPlay Early Power Estimator User Guide For Stratix III and Stratix IV FPGAs (1 MB)
- Stratix III Programmable Power (ver 1.1, May 2007, 632 KB)
- AN 454: Implementing PLL Reconfiguration in Stratix III Devices (ver 1.1, Oct 2007, 543 KB)
Design Example 1 (364 KB)
Design Example 2 (211 KB)
- AN 465: Implementing OCT Calibration in Stratix III Devices (ver 1.0, Nov 2007, 623 KB)
Design Example 1 (200 KB)
Design Example 2 (74 KB)
Design Example 3 (211 KB)
Stratix III OCT Power Up Example (46 KB)
- AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices (ver 1.0, Oct 2007, 391 KB)
- AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices (ver 1.0, May 2008, 1 MB)
- AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines (ver 1.0, Jun 2008, 918 KB)
- Stratix III Early SSN Estimator User Guide (ver 1.0, Jun 2008, 2 MB)
Stratix III Early SSN Estimator (631 KB)
- Stratix III FPGA Signal Integrity (ver 1.0, Nov 2006, 797 KB)
- AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices (ver 1.1, Jul 2008, 1 MB)
Design Example for AN 461 (2 MB)
- AN 469: Stratix III Design Guidelines (ver 1.1, May 2008, 628 KB)
- AN 504: DSP System Design in Stratix III Devices (ver 1.0, Feb 2008, 1 MB)
Design Example 1: Parallel FIR (79 KB)
Design Example 2: Multi-Channel FIR (20 KB)
Design Example 3: MAC_FIR (vhdl) (21 KB)
Design Example 4: Large Mult_Add (11 KB)
- AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines (ver 1.0, Jun 2008, 918 KB)
- Designing High-Performance DSP Hardware Using Catapult C Synthesis and the Altera Accelerated Libraries (ver 1.0, Oct 2007, 687 KB)
- Hardware/Software Co-Verification Using FPGA Platforms (ver 1.0, Aug 2008, 754 KB)
- Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
- Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
- Stratix_III_Advertorial (ver 1.0, Aug 2007, 98 KB)
- 1080p video framework from Altera (ver 1.0, Apr 2008, 230 KB)
- Accelerating applications on coprocessing platforms (ver 1.0, Jul 2007, 104 KB)
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
- Altera wireless solutions - 3GPP Long-Term Evolution (ver 1.0, Jan 2008, 68 KB)
- Broadcast Solutions Supporting Altera's HD Quality Initiative (HDQI) (ver 2.0, Apr 2008, 2 MB)
- Development boards for broadcast applications (ver 2.0, Apr 2008, 122 KB)
- HardCopy ASICs (ver 1.1, Jul 2008, 277 KB)
- Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
- Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
- Altera's Strategy for Delivering the Benefits of the 65-nm Semiconductor Process (ver 1.1, Sep 2006, 345 KB)
- Design Security in Stratix III Devices (ver 1.4, Nov 2006, 288 KB)
- Designing and Using FPGAs for Double-Precision Floating-Point Math (ver 1.1, Aug 2007, 683 KB)
- FPGA Performance Benchmarking Methodology (ver 1.6, Aug 2007, 246 KB)
- Guidance for Accurately Benchmarking FPGAs (ver 1.2, Dec 2007, 848 KB)
- HardCopy ASICs (ver 1.1, Jul 2008, 277 KB)
- Performing Equivalent Timing Analysis Between Altera Classic Timing Analyzer and Xilinx Trace (ver 3.0, Oct 2007, 1 MB)
- Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace (ver 1.0, Nov 2007, 1 MB)
- Robust SEU Mitigation With Stratix III FPGAs (ver 1.0, Feb 2007, 801 KB)
- SEmulation: Turbocharging the FPGA Development Process (ver 1.0, Mar 2007, 1 MB)
- Single- and Dual-Clock FIFO Megafunction User Guide (ver 4.0, May 2007, 960 KB)
dcfifo_in_legacy_mode.qar (Example 3) (268 KB)
dcfifo_in_show_ahead_mode.qar (Example 4) (224 KB)
dcfifo_narrow_write_wide_read.qar (Example 6) (228 KB)
dcfifo_wide_write_narrow_read.qar (Example 5) (232 KB)
scfifo_in_legacy_mode.qar (Example 1) (36 KB)
scfifo_in_show_ahead_mode.qar (Example 2) (38 KB)
- Stratix III FPGAs (ver 1.2, Aug 2007, 2 MB)
- Stratix III FPGAs vs. Xilinx Virtex-5 Devices: Architecture and Performance Comparison (ver 2.1, Oct 2007, 949 KB)
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