Literature Licensing Buy On-Line Download Entire Site Part Number Knowledge DB

Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line

Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature

FPGAs       Stratix IV (E and GX)       Stratix III       Stratix II       Stratix       Stratix GX       Stratix II GX       Arria GX       Cyclone III       Cyclone II       Cyclone     CPLDs       MAX II       MAX 3000A       MAX 7000     ASICs       HardCopy III       HardCopy II       HardCopy     By End Market       Automotive       Broadcast       Consumer       Medical     Configuration       Configuration Devices     Mature Products       Product Listing     Design Software       Quartus II       System-Level Software       MAX+PLUS II     IP/Embedded Processors    IP Megafunctions       Nios II Processor       Nios Processor       SOPC Builder     By Technology    Technologies     By Type       Application Briefs       Application Notes       Conference Papers       Data Sheets       Device Pin-Outs       Errata Sheets       Functional Specifications       Manuals       Release Notes       Technical Briefs       User Guides       White Papers     General Documentation       Annual Reports       Brochures       Customer Notifications       Design Contest Papers       Glossary of Altera Terms       Inserts and Advertorials       Reliability Report       SEC Filings       Selector Guides       Sparkle Sheets     Email/E-Newsletter Sign Up       Subscribe Now       Manage Your Subscriptions       View E-Newsletter Archives       News & Views Ezine     Literature Update Sign Up       Subscribe Now       Manage Your Subscriptions       View Recent Updates       FAQ     RSS/XML News Feeds       Subscribe Now

Home > Products > Literature > Stratix II GX Print This Page Subscribe to Email Stratix II GX Handbook The Stratix® II GX Device Handbook is comprised of two volumes. Volume 1 is the Stratix II GX FPGA family data sheet. Volume 2 includes the Stratix II GX Transceiver User Guide. Volume 2 also provides detailed information on Stratix II GX features and PCB layout guidelines. To view both volumes, click the link below. Get more information on Stratix II GX Pin-Outs. Get more information on pin connection guidelines. Check the Knowledge Database for Known Issues with the Stratix II GX Handbook. Stratix II GX Device Handbook (Complete Two-Volume Set) (19 MB) Volume 1 (ver 4.3, Oct 2007, 4 MB) Section I. Stratix II GX Device Family Data Sheet (4 MB) Chapter 1. Introduction (ver 1.6, Oct 2007, 116 KB) Chapter 2. Stratix II GX Architecture (ver 2.2, Oct 2007, 2 MB) Chapter 3. Configuration & Testing (ver 1.4, Oct 2007, 186 KB) Chapter 4. DC & Switching Characteristics (ver 4.5, Oct 2007, 2 MB) Chapter 5. Reference & Ordering Information (ver 1.3, Oct 2007, 87 KB) Volume 2 (ver 4.3, Oct 2007, 15 MB) Section I. Stratix II GX Transceiver User Guide (10 MB) Chapter 1. Stratix II GX Transceiver Block Overview (ver 2.4, Oct 2007, 137 KB) Chapter 2. Stratix II GX Transceiver Architecture Overview (ver 4.2, Oct 2007, 2 MB) Chapter 3. Stratix II GX Dynamic Reconfiguration (ver 1.1, Oct 2007, 2 MB) Chapter 4. Stratix II GX ALT2GXB Megafunction User Guide (ver 4.2, Oct 2007, 5 MB) Chapter 5. Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide (ver 1.4, Oct 2007, 356 KB) Chapter 6. Specifications & Additional Information (ver 3.1, Oct 2007, 238 KB) Section II. Clock Management (2 MB) Chapter 7. PLLs in Stratix II & Stratix II GX Devices (ver 4.5, Oct 2007, 2 MB) Section III. Memory (685 KB) Chapter 8. TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX Devices (ver 4.5, Oct 2007, 381 KB) Chapter 9. External Memory Interfaces in Stratix II & Stratix II GX Devices (ver 4.5, Oct 2007, 405 KB) Section IV. I/O Standards (735 KB) Chapter 10. Selectable I/O Standards in Stratix II & Stratix II GX Devices (ver 4.6, Oct 2007, 513 KB) Chapter 11. High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX Devices (ver 2.3, Oct 2007, 353 KB) Section V. Digital Signal Processing (DSP) (320 KB) Chapter 12. DSP Blocks in Stratix II & Stratix II GX Devices (ver 2.2, Oct 2007, 338 KB) Section VI. Configuration & Remote System Upgrades (1 MB) Chapter 13. Configuring Stratix II & Stratix II GX Devices (ver 4.5, Oct 2007, 997 KB) Chapter 14. Remote System Upgrades with Stratix II & Stratix II GX Devices (ver 4.5, Oct 2007, 293 KB) Chapter 15. IEEE 1149.1 (JTAG) Boundary Scan Testing for Stratix II & Stratix II GX Devices (ver 3.3, Oct 2007, 273 KB) Section VII. PCB Layout Guidelines (469 KB) Chapter 16. Package Information for Stratix II & Stratix II GX Devices (ver 4.3, May 2007, 480 KB) Related Documentation Data Sheets Altera Device Package Information Data Sheet (ver 15.1, May 2008, 4 MB) Stratix Series Device Thermal Resistance (ver 4.0, Jan 2008, 164 KB) User Guides External DDR Memory PHY Interface Megafunction User Guide (ALTMEMPHY) (ver 5.0, Jul 2008, 2 MB) DDR Timing Wizard User Guide (ver 3.0, Nov 2007, 2 MB) Stratix II GX Early SSN Estimator User Guide (ver 1.0, Aug 2007, 350 KB) Stratix II GX Early SSN Estimator ( 357 KB) PCI Express Development Kit, Stratix II GX Edition Getting Started User Guide (ver 1.0.2, Apr 2007, 1 MB) PowerPlay Early Power Estimator User Guide for Stratix II, Stratix II GX, and HardCopy II (ver 1.2, Jan 2007, 3 MB) Transceiver SI Development Kit, Stratix II GX Edition Getting Started User Guide (ver 1.0, Jun 2006, 594 KB) Manuals Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board Reference Manual (ver 1.0, Jun 2006, 864 KB) Application Notes AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices (ver 5.1, May 2008, 2 MB) AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices (ver 2.2, Jul 2008, 881 KB) AN 408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines (ver 2.1, Jul 2008, 4 MB) SII Simulation Example ( 3 KB) SIII Simulation Example ( 3 KB) AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction (ver 1.2, May 2008, 888 KB) Example Design for AN 462: top.qar ( 2 MB) AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (ver 4.0, Nov 2007, 3 MB) ALTMEMPHY Example ( 3 MB) Legacy PHY Example ( 5 MB) AN 449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices (ver 1.2, Sep 2007, 284 KB) AN 472: Stratix II GX SSN Design Guidelines (ver 1.0, Aug 2007, 666 KB) AN 339: Serial Digital Interface Demonstration for Stratix II GX Devices (ver 3.3, May 2007, 288 KB) AN 366: Understanding I/O Output Timing for Altera Devices (ver 1.0, Jul 2006, 311 KB) White Papers Hardware/Software Co-Verification Using FPGA Platforms (ver 1.0, Aug 2008, 754 KB) Floating-Point Compiler: Increasing Performance With Fewer Resources (ver 1.0, Nov 2007, 542 KB) Using Stratix II GX in HDTV Video Production Applications (ver 2.0, Sep 2005, 106 KB) Brochures Stratix II GX Brochure (ver 1.0, Oct 2007, 131 KB) Selector Guides Altera Product Catalog (ver 5.0, Jul 2008, 2 MB) Stratix FPGA Series Package & I/O Matrix (ver 1.0, Aug 2006, 75 KB) Errata Sheets Stratix II GX FPGA Family Errata Sheet (ver 1.2, Sep 2007, 133 KB) Technical Briefs TB 092: Power Distribution Network (ver 1.0, Oct 2007, 786 KB) (High-Speed Board Design Advisor) TB 093: Thermal Management (ver 1.0, Oct 2007, 235 KB) (High-Speed Board Design Advisor) TB 094: Pinout Definition (ver 1.0, Oct 2007, 381 KB) (High-Speed Board Design Advisor) TB 095: High-Speed Channel Design and Layout (ver 1.0, Oct 2007, 2 MB) (High-Speed Board Design Advisor) TB 096: Hardware Integration, Test, and Debug (ver 1.0, Oct 2007, 290 KB) (High-Speed Board Design Advisor) Product Overview 1080p video framework from Altera (ver 1.0, Apr 2008, 230 KB) 3-Gbps Serial Digital Interface (ver 2.0, Apr 2008, 1 MB) Broadcast Solutions Supporting Altera's HD Quality Initiative (HDQI) (ver 2.0, Apr 2008, 2 MB) Development boards for broadcast applications (ver 2.0, Apr 2008, 122 KB) Altera wireless solutions - 3GPP Long-Term Evolution (ver 1.0, Jan 2008, 68 KB) Stratix II GX FPGAs (ver 1.0, Oct 2007, 112 KB) Inserts and Advertorials Protecting IP Through FPGA Design Security (ver 1.0, Oct 2006, 933 KB) (advertorial) Stratix II GX: Transceivers with Integrity Advertorial (ver 1.0, Apr 2006, 563 KB) Rate This Page

Please Give Us Feedback

Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On-Line  Devices | Design Software | Intellectual Property | Design Services | Dev. Kits/Cables | Literature  Contact Us | Site Help | Site Map | Privacy | Legal Notice  Copyright © 1995-2008 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation