Radar and Sensors
Modern warfare in urban and coastal environments depends heavily upon situational awareness. Soldiers in the air, at sea, and on the ground need to understand the environment around them and identify threats as early as possible. State-of-the-art military advanced sensors (see Figure 1) have unprecedented requirements regarding the vast amount of environmental data to be measured and processed. To handle this data and provide “actionable intelligence” to the soldier as soon as possible, sensor system logic requires optimized logic and digital signal processing (DSP) density, high-speed transceivers, power-versus-performance design flexibility, and high-assurance design flow to meet end-user requirements.
Figure 1. Digital Convergence of Radar, Electronic Warfare, and Electro-Optical Systems
Notes:
- EO = electro-optical
- ACS = aerial common sensor
High-speed signal processing is critical to the function of advanced sensor systems. To meet the demands of radar and sensor system designs, Altera offers digital signal processing (DSP) power in its high-density Stratix® series FPGAs and HardCopy® ASICs.
Advanced Sensor Requirements
The challenges in military advanced sensor design are unique compared to other engineering fields. All of the design constraints of the commercial marketplace apply, plus sustainability, rigorous test and verification, and extended design and implementation life cycles that occur over the course of two or three generations of component technology. Some examples of these constraints are:
- High serial data-streaming capacity—Digital antenna technology moves analog-to-digital conversion closer to the receiver and requires more signal resolution to perform digital filtering.
- Complex math operations—Signal pre-processing and matrix operations require large numbers of DSP block elements to assume the roles traditionally filled by digital signal processors.
- Sensitivity to heat dissipation—Sensor systems often have a long, if not continuous, mission life, requiring the dissipation of heat from continuous operation.
- Logic density for multi-role electronics—With so many military missions being performed with the same array, logic requirements are extremely high in transmit and receive electronics.
- Speed and latency performance—The speed grade and latency of the logic devices in a sensor array (see Figure 2), as well as all the latency of interfaces between logic devices, affect the reaction times and beam forming algorithm performance.
- Parts availability—Sensor systems are very complex, and the impact of even one part being received behind schedule can have expensive consequences for the rest of the system.
- Tool-flow ease-of-use—As millions of logic elements (LEs) are integrated into a system design, the design, compilation, and test of large pieces of logic code is a substantial driver of both cost and schedule.
- Signal integrity—As more receiver elements provide data to be correlated with one another in final processing, small signal errors have larger impacts on sensor algorithms. Signal integrity in digital LEs is therefore paramount.
Figure 2. Sensor Array Block Diagram
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Notes:
- RF = radio frequency
- LO = local oscillator
Military electronics are converging on most platforms, requiring common hardware to perform a variety of missions with an "open systems" interface approach and requiring configurable hardware that enables rapid prototyping and configuration changes. In addition, larger and more flexible logic devices are needed to reduce component count and incorporate the growing number of military user requirements.
Altera's 40-nm Stratix IV FPGAs are designed to provide product leadership in radar and advanced sensor technologies. With over 200 Gbytes of I/O capability, large DSP counts, excellent signal integrity, highly scalable embedded processing blocks, and logic density leadership up to 680K LEs, Stratix IV FPGAs offer true system-on-a-programmable-chip (SOPC) possibilities to military sensor designs.
Prototyping on FPGA, Shipping on ASIC
With the availability of HardCopy® IV GX ASICs with high-speed transceivers, designers of radar and sensor systems have more options for high-speed logic.
Systems can be designed, prototyped, and tested using high-speed Stratix IV GX FPGAs. Then, at the time of deployment or low-rate initial production, a trade-off can take place between Stratix IV GX FPGAs and HardCopy IV GX ASICs. HardCopy ASICs can reduce power by about 50 percent, increase speed performance, and add single event upset (SEU) immunity to a system. Transitioning from FPGA to ASIC, using Altera’s design flow, costs less than 20 percent of traditional ASIC design and requires no additional design tools outside of the Quartus® II software.
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