Training Partner Profile: Bauman Moscow State Technical University
Bauman Moscow State Technical University is a certified member of the Altera® Training Partner Program (ATPP), enabling them to provide engineers with high-quality training on Altera's products. All certified ATPP members get regular information updates from Altera to ensure they have the tools to teach Altera's latest technologies. Classes are usually taught in the local language. For further information and pricing, contact:
Overview
The Information Systems and Telecommunications Department (IU3) at Moscow State Technical University n.a. Bauman (Bauman MSTU) prepares specialists in the areas of telecommunications, data acquisition and processing, and industrial control. The department is connected with many Russian companies and scientific institutes in these areas. We provide courses for both our students and engineers.
In 1998, the Altera® Training Center was established in cooperation with Fulcrum Corporation. Since then, over 300 engineers from leading Russian companies have studied our courses.
Bauman has extensive experience in the development of data acquisition systems, telemetry systems, digital signal processing (DSP) systems, application-specific boards, and external devices for the PC. Our engineers provide consulting and development services.
Technology expertise includes:
- Buses and interfaces
- PCI, LVDS
- Digital signal processing
- DSP blocks (filters, transforms) in FPGAs
- Coding
- Block and convolutional coders/encoders (CODECs)
- DSP, microcontroller systems, intellectual video, image processing
Locations for Instructor-Led Training
Bauman provides the following instructor-led courses in Moscow, Russia.
| Course Name |
Description |
| Quartus® II Software: Design Techniques for Altera Programmable Logic Devices |
The following is a brief description of the course contents:
- Overview of MAX®, MAX II and Cyclone® II families
- Quartus II software and tools overview
- Basic FPGA design flow;
- HDL introduction (AHDL or Verilog)
- Entering and controlling design settings (analysis and synthesis settings, fitter settings, timing requirements)
- Recommended FPGA design guidelines
Students will create several projects starting from simple, step-by-step project creation and ending with a fully functional project that can be downloaded to an FPGA.
|
| Nios II Processor: System on Chip Design in Altera Devices |
The following is a brief description of the course contents:
- Nios® II architecture
- SOPC Builder
- Software development in Nios II IDE
- Project debugging
Students will learn how to create Nios II-based projects in the Quartus II software and develop software in the Nios II IDE.
|
Contact Information
Bauman MSTU
IU3 department
2nd Baumanskaya Street, 5
105005 Moscow
Russia
Phone: +7-495-263-62-86
Fax: +7-495-267-65-37
Email: altera@iu3.bmstu.ru
http://iu3.bmstu.ru/altera/
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